---
title: "Line codes"
question: "Why do fast serial links use line codes like 8b/10b?"
url: "https://nearfieldnotes.com/videos/line-codes/"
site: "Near Field Notes"
video: "https://nearfieldnotes.com/media/line-codes/full.mp4"
duration: "3:07"
date: "2026-11-08"
note: "https://nearfieldnotes.com/notes/line-codes/"
---

# Line codes (video)

Why do fast serial links use line codes like 8b/10b?

3:07, with sound. [Read Note 26](https://nearfieldnotes.com/notes/line-codes/) for the full answer, with figures, conditions and sources.

## Transcript

SATA runs at 6 Gb/s. Divide by 8, and you'd expect 750 MB/s.

The link tops out at 600.

Every 8 bits of data go out on the cable as 10.

A link this fast has no clock wire. The receiver finds each bit from the edges in the data.

And each wire has a capacitor in series, which blocks DC.

I simulated a 4 KB block of zeros, sent as plain bits through SATA's 12 nF caps.

With no edges, the receiver's clock has nothing to lock to.

And the capacitor charges, until the signal sinks to the threshold, where a 1 and a 0 look the same.

A line code reshapes the bits, so there are always edges and no DC.

The classic is 8b/10b, published by IBM in 1983.

It only uses 10-bit patterns with plenty of edges: never more than 5 identical bits in a row.

It also counts ones against zeros. When one side gets ahead, the next symbol leans back the other way.

The zeros from before now stay centered.

And one 7-bit pattern, the comma, can never appear in data. The receiver uses it to find where every byte starts.

PCIe 1 and 2, USB 3, DisplayPort 1, gigabit Ethernet over fiber, and Fibre Channel all used it. SATA still does.

But 20% got expensive. 10-gig Ethernet on 8b/10b took four lanes at 3.125 GBd.

The one-lane version, in 2002, used 64b/66b instead.

It scrambles 64 data bits and puts a 2-bit header in front, always 01 or 10.

That guarantees an edge in every block, and shows the receiver where blocks start.

The scrambler makes long runs unlikely, but not impossible. The longest possible run is 66 bits.

PCIe 3.0 tried 10 GT/s first. It was too hard on boards and power.

So it stayed at 8 and swapped 8b/10b for 128b/130b. Usable speed still nearly doubled.

Scramblers can be beaten. In the 90s, crafted packets could knock SONET links out of sync. A second scrambler fixed it in 1999.

USB 3.1 Gen 2 picked 128b/132b. Its overhead is 3%, exactly the same as 64b/66b.

USB spent the extra bits on a 4-bit header, 0011 or 1100. They differ in every bit, so one flipped bit gets corrected.

DisplayPort 2 and USB4 use it too. HDMI 2.1 went with its own 16b/18b.

PCIe 6.0 doubled again by sending four voltage levels instead of two.

The levels sit closer together, so the allowed raw error rate went from one in a trillion bits to one in a million.

So it dropped the block code. Data moves in 256-byte flits, with error correction and a CRC.

It still scrambles, so the edges are still there.

And the overhead went back up, to about 8% of every flit.

400-gig Ethernet spends about 6% on coding and error correction. USB4 v2 packs 11 bits into 7 symbols, each with 3 levels.

20%, then 3, then 1.5, and back up to 8 once error correction moved in.

SATA never left 8b/10b. That's why 6 gigabits still means 600 megabytes.

---

Source: https://nearfieldnotes.com/videos/line-codes/