---
title: "What is zero-voltage switching, and what does it save?"
topic: "Zero-voltage switching"
answer: "Turning a switch on only after a current has already pulled the voltage across it to zero. A pair of 80 V FETs switching 10 A at 48 V then loses 0.45 µJ per turn-on, instead of 2.6 µJ."
url: "https://nearfieldnotes.com/notes/zvs/"
site: "Near Field Notes"
author: "Michael Walker"
note: 10
family: "Power"
published: "2026-11-03"
revised: "2026-11-03"
revision: 1
video: "https://nearfieldnotes.com/videos/zvs/"
---

Note 10 · [Power](https://nearfieldnotes.com/families/power/) · Rev 1 · [Watch the video · 2:09](https://nearfieldnotes.com/videos/zvs/)

Zero-voltage switching

# What is zero-voltage switching, and what does it save?

**Short answer:** Turning a switch on only after a current has already pulled the voltage across it to zero. A pair of 80 V FETs switching 10 A at 48 V then loses 0.45 µJ per turn-on, instead of 2.6 µJ.

The figure turns one FET on twice. Hard, it takes on the current while 48 V is still across it, and for a few nanoseconds it heats at up to 860 W.

At zero volts, a current drains that voltage away before the gate comes on. By the time the FET conducts, there is almost nothing across it to turn into heat.

**Note 10’s opening figure: One FET turning on.** Hard, then at zero volts

![Note 10’s opening figure: One FET turning on](https://nearfieldnotes.com/notes/zvs/fig-opening.png)

*What the figure shows:* One TPN19008QM turning on at 48 V, twice: the FET with the current through it, and below, the voltage across it, the current through it and the power heating it. Hard: the voltage stays at 48 V until the gate comes on at 50 ns, then the current climbs to 26 A with the voltage still across it and the FET heats at up to 860 W. Zero-voltage: a current flows out of the FET first, through its capacitance and then its body diode, so the voltage is already zero when the gate comes on; the current then turns around and climbs to 10 A, and the FET never heats past 10 W.

A TPN19008QM, its gate driven from 10 V through 10 Ω. Hard, 10 A comes into it. At zero volts, a 0.4 µH inductor first pulls 10 A out of it, then turns around. 0 ns is the switch above it letting go.

## Where the FET sits

*The cell inside most converters*

The FET never works alone. Most power converters pair it with a second switch and pass an inductor’s current back and forth between the two.

Only one switch is on at a time. Between turns comes a short [dead time](https://nearfieldnotes.com/glossary/#g-dead-time), here 50 ns, when both are off and the inductor’s current has to find its own way.

Each switch also has [capacitance](https://nearfieldnotes.com/glossary/#g-coss) across it, drawn as C. At 48 V the pair holds `Q = 33.5 nC`, and turning a switch on means moving that charge.

The way the inductor’s current flows as the upper switch lets go decides how the lower one turns on. Flowing into the node, the current holds it at 48 V, so the lower switch turns on hard.

Flowing out of the node, the current drains the lower switch’s C and fills the upper one’s. The voltage falls to zero by itself, before the gate comes on.

**Fig. 10: The switching cell.**

![Fig. 10: The switching cell](https://nearfieldnotes.com/notes/zvs/fig-10.png)

*What the figure shows:* Figure 10: the switching cell. A 48 V supply with a capacitor across it, and two switches in series across it, the other switch on top and the switch below. Each has its own capacitance C across it. From the node between them an inductor L runs to the load. Its current flows into the node for a hard turn-on of the switch, and out of it for a zero-voltage one.

Both switches are TPN19008QM, 80 V FETs, with their gates left out. The arrows are the two ways the inductor’s current can flow as the upper switch lets go.

## A capacitance that changes with voltage

*Both switches, from the fitted model*

The C in Fig. 10 isn’t one number. A FET’s capacitance is largest near zero volts and falls as the voltage across it rises, in this one from 783 pF at 1 V to 227 pF at 48 V.

That’s why this page counts charge instead. Q adds the capacitance up over every volt the switch swings through, for both switches:

`Q = 2 ∫_0^(48 V) C dV`

where Q: charge in both switches’ capacitance at 48 V (C); C: one switch’s capacitance at that voltage (F); V: voltage across one switch (V).

`= 2 × 16.7 nC = 33.5 nC`

**Fig. 10b: The capacitance at the node.**

![Fig. 10b: The capacitance at the node](https://nearfieldnotes.com/notes/zvs/fig-10b.png)

*What the figure shows:* Figure 10b: capacitance at the node against the voltage across the lower switch, 0 to 48 V. The lower switch's own falls from 897 pF at 0 V to 227 pF at 48 V. The upper switch's is the same curve flipped. Together they are symmetric about 24 V: 1,012 pF at 1 V and at 47 V, 597 pF at 24 V. Below, one switch's charge against its voltage, reaching 16.7 nC at 48 V. The energy it stores, 0.32 µJ, is the area between that curve and the charge axis. A fixed capacitor holding the same charge would follow a straight line and store 0.40 µJ.

The upper switch has 48 V less whatever the lower one has, so its curve is the lower one’s, flipped. Below, the energy one switch stores is the shaded area, 0.32 µJ. A fixed capacitor holding the same charge would follow the dashed line and store the whole triangle, 0.40 µJ.

Output capacitance

### Half of QV, whatever the curve

**Field marks.** App notes model the curve as `C = C_oss (V_oss / V)^n`, with n between ⅓ and ½. This FET’s fitted model follows n = 0.37.

**Look-alike.** The energy a capacitance stores, `E = ∫_0^(48 V) V C dV`, is the shaded area in Fig. 10b. It’s less than ½QV because most of the capacitance sits at low voltage, so both switches together store 0.65 µJ at 48 V.

**Range.** Together the two curves are symmetric about 24 V, 1,012 pF at 1 V and at 47 V. On average the charge moves against half the supply, so moving Q costs ½QV, 0.80 µJ, whatever the curve’s shape.

**Habitat.** A hard turn-on burns that ½QV in its channel. A zero-voltage swing borrows it from the current instead.

## Where a hard turn-on loses energy

*10 A into the node, and out of it*

Start with the hard turn-on, the one most converters make every cycle. Its 2.6 µJ comes from four places, and turning on at zero volts removes three of them.

**Fig. 10c: Where it goes.**

![Fig. 10c: Where it goes](https://nearfieldnotes.com/notes/zvs/fig-10c.png)

*What the figure shows:* Figure 10c: where each turn-on's energy goes, in µJ. Hard: 2.6 µJ in all, overlap 1.17, capacitance 0.80, diode recovery 0.24, dead time 0.36. Zero-voltage: 0.45 µJ in all, overlap 0.02, dead time 0.43.

Both switches’ heat. Diode recovery is the difference from the same turn-on run with a body diode that stores no charge.

Hard switching

### Four costs, three avoidable

**Field marks.** For a few nanoseconds the switch carries current with voltage still across it: 1.2 µJ. The textbook sketch, `E = ½ V I (t_i + t_v)`, gives 2.1 µJ, but the loop’s inductance lets the voltage start falling early.

**Look-alike.** Turning on also empties the switch’s capacitance and refills the other’s through its channel: `½ Q V = 0.80 µJ`. With no current at all, the turn-on still loses 0.84 µJ.

**Range.** Through the dead time the other switch’s [body diode](https://nearfieldnotes.com/glossary/#g-body-diode) carried the current, 0.36 µJ. Its stored charge then comes out at full voltage, 0.24 µJ.

**Habitat.** At zero volts nearly all that’s left is the dead time, 0.43 µJ. It goes to the other switch letting go and to this one’s own diode.

## Why a faster gate can’t fix it

*The hard turn-on at six gate resistors*

The usual fix for switching loss is a faster gate. Driving it through less resistance shortens the overlap, so the loss falls from 6.5 µJ at 47 Ω to 2.0 µJ at 1 Ω.

Then it stops falling. A faster gate can’t shrink the capacitance’s ½QV or the dead time, and the diode’s recovery grows. The faster edge also makes the other switch ring to 81 V, past its 80 V rating.

Getting under that floor takes a different idea: get rid of the voltage before the switch turns on.

**Fig. 10d: Gate resistor against loss.**

![Fig. 10d: Gate resistor against loss](https://nearfieldnotes.com/notes/zvs/fig-10d.png)

*What the figure shows:* Figure 10d: the hard turn-on at gate resistors from 1 to 47 Ω. 1 Ω: 2.0 µJ lost, the other switch peaks at 81 V. 2.2 Ω: 1.9 µJ lost, the other switch peaks at 81 V. 4.7 Ω: 2.0 µJ lost, the other switch peaks at 81 V. 10 Ω: 2.6 µJ lost, the other switch peaks at 53 V. 22 Ω: 3.9 µJ lost, the other switch peaks at 48 V. 47 Ω: 6.5 µJ lost, the other switch peaks at 48 V. Half of Q times V, the capacitance alone, is 0.80 µJ. The FET is rated 80 V.

The hard turn-on at 48 V and 10 A. The gate always turns off through 2 Ω.

## How a current empties the switch

*1 A out of the node, 50 ns of dead time*

Run the inductor’s current out of the node and it does that for the switch. Here is the turn-on with just 1 A, slow enough to watch.

1. **Let go.** The other switch turns off.
2. **Swing.** The current pulls the charge out of the switch and into the other one, at a steady rate.
3. **Diode.** At zero the switch’s own body diode catches the current.
4. **On.** The gate comes on with nothing across the switch.

The swing moves Q at the rate the current flows, so the time it takes is

`t = Q/I`

where t: time the swing takes (s); Q: charge in both switches’ capacitance at 48 V (C); I: current that swings the node (A).

`= (33.5 nC)/(1 A) = 33.5 ns`

Simulated, the swing takes 32.4 ns. Its energy goes back into the current instead of into heat.

Q already adds the capacitance up over every volt, so the rule holds whatever the curve’s shape.

The opening’s current was 10 A, so its swing took only 4.0 ns.

**Fig. 10e: One zero-voltage turn-on.**

![Fig. 10e: One zero-voltage turn-on](https://nearfieldnotes.com/notes/zvs/fig-10e.png)

*What the figure shows:* Figure 10e: the switch turning on at zero volts with 1 A flowing out of the node and 50 ns of dead time, with the cell drawn at each step and the current's path through it lit. 1: the other switch lets go, the current still coming through its channel. 2: the current pulls the node from 48 V to zero in 32.4 ns, a straight ramp, drawing on both switches' capacitance. 3: the switch's own body diode carries the 1 A. 4: the gate comes on at 50 ns with nothing across the switch, and its channel carries the current.

Negative current flows backward through the switch, out of the node.

## How much current it takes

*Every current against three dead times*

The swing has to finish inside the dead time, or the switch turns on with voltage still across it. That sets the least current that will do.

Too little leaves voltage for the turn-on to burn. Too much only keeps the diode conducting longer, which is why 10 A loses more than 1 A.

**Note 10’s explorer: Enough current.**

![Note 10’s explorer: Enough current](https://nearfieldnotes.com/notes/zvs/fig-explore.png)

*What the figure shows:* Voltage across the switch for the chosen current and dead time, with the moment its gate comes on marked.

Out means the current leaves the node, the zero-voltage way. 10 A in is the hard turn-on. The least lost here is 0.01 µJ, at 0.5 A with 100 ns.

## When an inductor makes the current

*1 µH, the switch held off*

So far the current held steady through the swing, as it does in a large inductor. A small inductor’s current falls as the voltage swings against it.

The swing then runs on the energy the inductor stores, and the rule becomes one of energy instead of time. The energy to cover is ½QV, 0.80 µJ, more than the 0.65 µJ the capacitances store.

**Fig. 10f: Three starting currents.**

![Fig. 10f: Three starting currents](https://nearfieldnotes.com/notes/zvs/fig-10f.png)

*What the figure shows:* Figure 10f: a 1 µH inductor swings the node down on its own, the switch held off. The swing needs 1.27 A. 1.14 A: lowest 4.0 V at 48 ns. 1.27 A: lowest 0.3 V at 48 ns. 1.60 A: lowest -0.7 V at 36 ns.

The inductor runs from the node to a steady 48 V, carrying its current out of the node until the other switch lets go at 0 ns. 1.14 A is what the stored-energy rule asks for, 1.27 A what ½QV asks for.

Resonant swing

### The inductor’s energy pays for the swing

**Field marks.** The swing reaches zero only if `½ L I^2 ≥ ½ Q V`. For 1 µH that means `I ≥ √(Q V / L) = 1.27 A`. Simulated, 1.27 A bottoms out 0.3 V short of zero.

**Look-alike.** Many app notes size the inductor by what the capacitances store instead, `½ L I^2 ≥ 2 E`, which asks for only 1.14 A. Simulated, that stops 4.0 V short and swings back up.

**Range.** At just enough current the swing takes a quarter of a resonant cycle, `t = π/2 √(L C)`. With C = Q/V that’s 41.5 ns. Simulated, 41.2 ns.

**Habitat.** The opening used 0.4 µH carrying 10 A, which stores 20 µJ, 25 times what the swing needs. Phase-shifted full bridges size their resonant inductor by energy too. TI’s SLUA107A counts what the capacitances store, the smaller figure.

## What it saves

*One turn-on every cycle*

A converter pays its turn-on loss every cycle, so the loss grows with switching frequency: `P = E f`.

At low frequency the two turn-ons cost little either way. Above a few hundred kilohertz the hard one costs more than carrying the current.

**Fig. 10g: Loss against frequency.**

![Fig. 10g: Loss against frequency](https://nearfieldnotes.com/notes/zvs/fig-10g.png)

*What the figure shows:* Figure 10g: the power lost to turn-ons against switching frequency, at one turn-on a cycle. Hard switching, 2.6 µJ a turn-on, passes the 1.5 W of carrying 10 A at 568 kHz. Zero-voltage, 0.45 µJ, passes it at 3.2 MHz.

The two turn-ons from the top of the page, 2.6 µJ and 0.45 µJ.

Zero-voltage switching

### Nearly six times the frequency for the same loss

**Field marks.** At 100 kHz a hard turn-on costs 0.26 W and a zero-voltage one 0.05 W. At 1 MHz, 2.6 W and 0.45 W.

**Look-alike.** Carrying 10 A through one switch or the other costs 1.5 W either way. Hard switching matches it at 568 kHz, zero-voltage at 3.2 MHz.

**Range.** Most of what’s left is diode conduction. Just enough current and a dead time to match get it down to 0.01 µJ.

**Habitat.** The current has to come from somewhere, and making it costs. An assist cell simulated on moteus-c1’s leg cut its turn-on from 1.6 µJ to 1.0 µJ, not to zero.

## Zero-voltage circuits

*Where the swinging current comes from*

Every turn-on on this page used a current that was already there. A real converter has to arrange one, and the key sorts the usual ways.

Key to zero-voltage circuits

### Where does the swinging current come from?

1. 1a The inductor’s current already flows out of the switch when the other lets go Free, like a buck’s low side
2. 1b It flows into the switch Go to 2
3. 2a A small inductor can let its current reverse every cycle Triangular current mode
4. 2b It can’t Go to 3
5. 3a A transformer is in the loop Go to 4
6. 3b There isn’t one An assist cell
7. 4a Its magnetizing current is big enough LLC, active-clamp flyback
8. 4b Its leakage inductance has to supply it Phase-shifted full bridge

Each still has to meet one of the two rules on this page: enough current to move Q inside the dead time, or, from a small inductor, enough energy.

#### Conditions

- **Switches:** Two Toshiba TPN19008QM, 80 V, with a model fitted by hand to the datasheet, as in [Note 4](https://nearfieldnotes.com/notes/gate-ringing/). At 48 V each holds 16.7 nC.
- **Driver:** An ideal 10 V source, on through 10 Ω, or 1 to 47 Ω in Fig. 10d, and off through 2 Ω, with 3 nH in each gate loop. 50 ns of dead time, 25 and 100 ns in the explorer.
- **Copper:** 1.3 nH from the 1 µF capacitor around the two switches
- **Current:** 10 A, held steady over the edge, into the node or out of it. In the opening’s zero-voltage pass, 0.4 µH to a steady 48 V instead, and 1 µH in Fig. 10f.
- **Heat:** The opening shows the lower FET’s own. Everywhere else it is both switches’.
- **Lost:** What both switches dissipate beyond carrying the current, from the other switch’s gate command until this one is on and settled 250 ns later. What their capacitance stores and gives back isn’t counted, and nor is the gate driver’s energy.
- **Solver:** ngspice, at 27 °C

Simulated only. Nothing on this page has been measured on a board yet.

#### Limits

- 81 V is the FET model’s breakdown. At gate resistors of 4.7 Ω and below the other switch’s ring reaches it, so its real peak would be higher.
- The model’s capacitance and body diode are fitted to the datasheet’s curves, not measured.
- A large inductor’s current changes a little over an edge. Here it is held steady.
- The overlap is what’s left of the hard turn-on’s loss after the other three parts.

#### Files

- zsim/general.py The switching cell, every run on this page and how the loss is counted
- gatesim/fets.py The fitted FET model, from [Note 4](https://nearfieldnotes.com/notes/gate-ringing/)

#### Sources

- [TI SLUA107A, phase-shifted full-bridge zero-voltage design](https://www.ti.com/lit/an/slua107a/slua107a.pdf)
- [Infineon, primary-side MOSFET selection for LLC](https://www.farnell.com/datasheets/2254390.pdf)
- [TI SLUA871, the active-clamp flyback](https://www.ti.com/lit/pdf/slua871)
- [Haider and others, zero-voltage triangular current mode, 2020](https://doi.org/10.1109/OJPEL.2020.3040036)
- [De Doncker and Lyons, US 5,047,913, the assist cell](https://patents.google.com/patent/US5047913A/en)
- Brendan Graham, ZVS critical primary current and effective drain-source capacitance
- [Kasper, Burkart, Deboy and Kolar, ZVS of power MOSFETs revisited, 2016](https://doi.org/10.1109/TPEL.2016.2574998)
- [ngspice, the circuit simulator](https://ngspice.sourceforge.io/)

What should the next note be? [Ask for one](https://nearfieldnotes.com/#ask-for-a-note)

---

Source: https://nearfieldnotes.com/notes/zvs/

Cite as: Michael Walker, “Zero-voltage switching”, Near Field Notes, Note 10, Rev 1, 3 Nov 2026. https://nearfieldnotes.com/notes/zvs/

Figures: free to reuse under CC BY 4.0 (https://nearfieldnotes.com/license/). Each one's image is linked under its name. Credit Michael Walker, Near Field Notes, and link the figure: this address plus #fig- and its number, like https://nearfieldnotes.com/notes/zvs/#fig-10.