---
title: "How do you read a TDR trace?"
topic: "TDR"
answer: "As a map of the route. Across is distance: on this board, every 11.8 ps of echo time is 1 mm of trace. Up is impedance: a dip is extra capacitance, and a bump is extra inductance or a broken return path. Read it with the edge your spec names. The CM5 IO board’s USB-A socket pins read 67 Ω with a 15 ps edge and 83 Ω with USB 3.0’s 50 ps, inside its 90 ± 15 Ω."
url: "https://nearfieldnotes.com/notes/tdr/"
site: "Near Field Notes"
author: "Michael Walker"
note: 16
family: "Signal integrity"
published: "2026-11-05"
revised: "2026-11-05"
revision: 1
video: "https://nearfieldnotes.com/videos/tdr/"
---

Note 16 · [Signal integrity](https://nearfieldnotes.com/families/si/) · Rev 1 · [Watch the video · 0:14](https://nearfieldnotes.com/videos/tdr/)

TDR

# How do you read a TDR trace?

**Short answer:** As a map of the route. Across is distance: on this board, every 11.8 ps of echo time is 1 mm of trace. Up is impedance: a dip is extra capacitance, and a bump is extra inductance or a broken return path. Read it with the edge your spec names. The CM5 IO board’s USB-A socket pins read 67 Ω with a 15 ps edge and 83 Ω with USB 3.0’s 50 ps, inside its 90 ± 15 Ω.

A TDR sends a fast step down a line and records what comes back. Every change in the line sends part of the step back, and the time it takes says where.

The figure follows a 15 ps step down the USB 3 receive pair of Raspberry Pi’s CM5 IO board.

**Note 16’s opening figure: A step down the route.** USB 3, from the USB-A socket to the CM5

![Note 16’s opening figure: A step down the route](https://nearfieldnotes.com/notes/tdr/fig-opening.png)

*What the figure shows:* A 15 ps step travels down the USB 3 receive pair of the CM5 IO board, seen from the side: through the socket, along the top layer, down a via pair to the bottom layer, up a second via pair and on to the CM5 module. Echoes run back from each change. Below, the TDR trace on the same scale: 67 Ω at the socket pins, 96 Ω and 95 Ω at the via pairs, about 91 Ω along the plain line.

Blue is the step going in. Orange is the echoes coming back, drawn 20 times brighter than the step’s front. The TDR sits 60 mm of fixture off the left edge, so each echo joins the trace when it gets back there. Side view along the route, thickness not to scale. The cable, plug and module are stand-ins.

**The numbers**

*What a 15 ps edge reads along the route, through 60 mm of fixture. A peak or dip can sit about 2 mm from the copper that causes it.*

| Place | Read at, mm from the pins | TDR reads |
|---|---|---|
| Socket pins | −1.2 | 67 Ω |
| Hole in the plane past the pins | 1.4 | 103 Ω |
| First via pair | 21.2 | 96 Ω |
| Plain line, bottom layer | 28 | 91 Ω |
| Second via pair | 51.2 | 95 Ω |

## What a TDR is

*A step, a scope and a line*

A TDR is a step source and a fast scope on the same wire. The step [rises](https://nearfieldnotes.com/glossary/#g-rise-time) in a few tens of picoseconds and runs down the line. Wherever the line’s impedance changes, part of it reflects.

The scope adds each echo to the step it sent. Its trace rises where the line’s impedance goes up and falls where it goes down. A fast trace is built to hold [one impedance](https://nearfieldnotes.com/glossary/#g-characteristic-impedance) all the way: 90 Ω for USB 3, 100 Ω for HDMI and DisplayPort. A flat trace means a clean route.

**Fig. 16: A TDR, as a circuit.**

![Fig. 16: A TDR, as a circuit](https://nearfieldnotes.com/notes/tdr/fig-16.png)

*What the figure shows:* Figure 16: a TDR as a schematic. A step source drives the line through 100 Ω. A scope watches the node between the resistor and the line. The line is a 90 Ω fixture, then the board's 90 Ω route, ending in the CM5's 90 Ω receiver.

The TDR drives the pair from two 50 Ω channels, so the line sees it as 100 Ω.

**The parts**

*Each part of the circuit, left to right.*

| Part | Value |
|---|---|
| Step source and its resistance | 100 Ω |
| Fixture | 90 Ω, 60 mm |
| Route on the board | 90 Ω, 76 mm |
| CM5 receiver | 90 Ω |

The route here is real. Raspberry Pi publishes the KiCad files of its CM5 IO board, a 4-layer, 1.6 mm board. Its USB 3 receive pair runs 76 mm from the USB-A socket to the CM5 module.

On the way it drops to the bottom layer through one via pair and comes back up through another. Every trace of the USB 3 route comes from that copper. The cable, the plug and the module have no design files here, so they’re stand-ins.

**Fig. 16b: The CM5 IO board.**

![Fig. 16b: The CM5 IO board](https://nearfieldnotes.com/notes/tdr/fig-16b.png)

*What the figure shows:* Figure 16b: the Raspberry Pi CM5 IO board's top copper, 160 by 90 mm. The USB 3 receive pair is lit: from the USB-A socket on the bottom edge it runs up the top layer, drops through a via pair to the bottom layer, comes back up through a second via pair and ends under the CM5 module.

Top copper from the board’s KiCad files. The receive pair is lit, dashed where it runs on the bottom layer. The dashed outline is where the CM5 plugs in.

**The route**

*The USB 3 receive pair, from the socket pins.*

| Stretch | Layer | Length |
|---|---|---|
| Socket pins to the first via pair | Top | 19.1 mm |
| Between the via pairs | Bottom | 30.15 mm |
| Second via pair to the module | Top | 27.2 mm |

## Reading the trace

*Up is impedance*

The scope measures how much of the step comes back. That share is the [reflection coefficient](https://nearfieldnotes.com/glossary/#g-reflection). Against the TDR’s own 100 Ω, it turns into impedance:

`Z = Z_TDR (1 + ρ)/(1 − ρ)`

where Z: impedance at that spot on the line (Ω); Z_TDR: the TDR’s own impedance (Ω); ρ: reflection coefficient: the share of the step that comes back (no unit).

`= 100 Ω × 0.802 / 1.198 = 67 Ω at the socket pins`

A step that comes back bigger pushes the trace up, a bump. One that comes back smaller pulls it down, a dip. Two shapes do most of the work.

**Fig. 16c: Six things on a line.**

![Fig. 16c: Six things on a line](https://nearfieldnotes.com/notes/tdr/fig-16c.png)

*What the figure shows:* Figure 16c: six TDR traces of a 90 Ω line with one thing 50 mm along it, at a 25 ps edge. Extra capacitance makes a dip, extra inductance a bump. A line of lower impedance steps down and stays. An open end shoots up, a short drops to zero, and a matched end stays flat.

A 90 Ω line with one thing 50 mm along it, seen with a 25 ps edge.

**The numbers**

*Each trace's lowest and highest reading, and where it ends up. The line is 90 Ω.*

| Thing at 50 mm | Lowest | Highest | After it |
|---|---|---|---|
| 0.35 pF to ground | 46 Ω | 90 Ω | 90 Ω |
| 0.8 nH in series | 90 Ω | 113 Ω | 90 Ω |
| 75 Ω from here | 75 Ω | 90 Ω | 75 Ω |
| Open end | 90 Ω | Off the top | Off the top |
| Short | 0 Ω | 90 Ω | 0 Ω |
| Matched end | 90 Ω | 90 Ω | 90 Ω |

Dip and bump

### A dip is extra capacitance, a bump extra inductance

**Field marks.** 0.35 pF to ground dips a 90 Ω line to 46 Ω. 0.8 nH in series bumps it to 113 Ω. Both come back to the line right after.

**Look-alike.** A step down that stays down is a stretch of lower impedance, like 75 Ω from there on. An open end shoots off the top, and a short drops to zero.

**Range.** Dips come from big pads, stubs and copper too close to ground. Bumps come from a broken return path: a gap in the plane, or a via with no ground via beside it. [Note 17](https://nearfieldnotes.com/notes/via-stubs/) shows what a stub costs a fast link.

## Time is distance

*Across is where*

Across, the trace is time. An echo goes out and back, so a spot down the line answers after twice its delay:

`x = t/(2 τ)`

where x: distance down the line, from the socket pins (mm); t: echo time, counted from the pins’ echo (ps); τ: delay of the line per length (ps/mm).

`= 226 ps / (2 × 5.91 ps/mm) = 19.1 mm to the first via pair`

On this board an echo takes 11.8 ps per mm of trace, there and back. The traces from here on are drawn against mm from the socket pins.

**Fig. 16d: A finger on the HDMI pair.**

![Fig. 16d: A finger on the HDMI pair](https://nearfieldnotes.com/notes/tdr/fig-16d.png)

*What the figure shows:* Figure 16d: a fingertip pressed on the CM5 IO board's HDMI pair at three places, 15, 45 and 80 mm from the receptacle. The TDR shows one dip to about 85 Ω for each, at 174, 523 and 939 ps.

A fingertip pressed flat on the pair at three places, seen with a 30 ps edge from the HDMI receptacle.

**The numbers**

*A fingertip on the 96.5 Ω HDMI pair, seen with a 30 ps edge. 11.74 ps of echo time per mm.*

| Finger at | Dip at | Echo time | Dip reads |
|---|---|---|---|
| 15 mm | 14.8 mm | 174 ps | 85 Ω |
| 45 mm | 44.6 mm | 523 ps | 85 Ω |
| 80 mm | 80 mm | 939 ps | 85 Ω |

Finger test

### A finger finds the spot

**Field marks.** A fingertip on the pair adds capacitance under it. The 96.5 Ω line dips to 85 Ω where it sits.

**Look-alike.** A dip that stays put while the finger moves is something on the board.

**Range.** Can’t tell where a bump is? Slide a finger along the trace and watch the dip move with it. At 15 mm it answers at 174 ps, and at 80 mm at 939 ps.

**Habitat.** The CM5 IO board’s HDMI0 data pair: 92 mm of top-layer trace from the receptacle to the module.

## The worst spot

*The USB-A socket*

Back on the USB 3 pair, the deepest feature sits at the socket, ahead of both via pairs.

**Fig. 16e: The socket, close up.**

![Fig. 16e: The socket, close up](https://nearfieldnotes.com/notes/tdr/fig-16e.png)

*What the figure shows:* Figure 16e: the USB-A socket close up, its pins through the board and the ground plane under the top layer, with a hole cut around the pins. The TDR there: a 15 ps edge dips to 67 Ω at the pins, then climbs to 103 Ω over the hole. A 50 ps edge reads 83 Ω and 92 Ω.

The ground plane just under the top layer. Pale is the hole cut around the pins. The outlined pins carry the pair, which leaves on the top layer.

**The numbers**

*What the TDR reads at the socket, through 60 mm of fixture.*

| Edge | Pins | Hole past the pins |
|---|---|---|
| 15 ps | 67 Ω | 103 Ω |
| 50 ps | 83 Ω | 92 Ω |

Socket pins

### The pins dip to 67 Ω

**Field marks.** With a 15 ps edge the socket pins read 67 Ω. Right after them the trace climbs to 103 Ω.

**Look-alike.** The dip is the pins: big pads, and copper-lined holes that run through the whole board as [stubs](https://nearfieldnotes.com/glossary/#g-via-stub). The bump is where the traces cross the hole cut in the ground plane around them.

**Range.** A 50 ps edge reads the same pins at 83 Ω, and the bump all but goes. [Note 1](https://nearfieldnotes.com/notes/ground-cut/) sizes a hole like this under USB-C pads.

**Habitat.** The USB-A receptacle, an MTCONN UBAF30-D2011 with through-hole pins.

## Break it on purpose

*Two what-ifs on the same route*

This board’s vias and planes are done right. Taking that away shows what each rule is worth.

**Fig. 16f: Ground vias.**

![Fig. 16f: Ground vias](https://nearfieldnotes.com/notes/tdr/fig-16f.png)

*What the figure shows:* Figure 16f: the via pair under the CM5, close up on the top layer, as built with ground vias beside the signal vias, and with the four nearest ground vias taken out. A 15 ps edge reads 96 Ω at the first via pair and 95 Ω at this one as built, and 98 Ω and 97 Ω without them.

The via pair under the CM5, on the top layer, seen with a 15 ps edge. Both via pairs on the route use this pair’s solve.

**The numbers**

*Highest reading at each via pair with a 15 ps edge.*

| Via pair | As built | Ground vias out |
|---|---|---|
| First, 19 mm from the pins | 96 Ω | 98 Ω |
| Second, 49 mm from the pins | 95 Ω | 97 Ω |

Ground vias

### A ground via beside every signal via

**Field marks.** Each signal via here has two ground vias within 1 mm. A 15 ps edge reads 96 Ω at the first via pair and 95 Ω at this one.

**Look-alike.** Take out those four ground vias and they read 98 Ω and 97 Ω. The return current has to detour to find a way between the planes, and that detour is inductance.

**Range.** Any via that moves a fast pair between layers with a ground plane on each side.

**Fig. 16g: A slot in the plane.**

![Fig. 16g: A slot in the plane](https://nearfieldnotes.com/notes/tdr/fig-16g.png)

*What the figure shows:* Figure 16g: a 0.5 mm slot cut across the ground plane under the bottom-layer pair, 41 mm from the socket pins. The line reads 91 Ω. Over the slot a 15 ps edge reads 98 Ω.

The bottom-layer pair and the ground plane next to it, with a 0.5 mm slot cut across the plane. Seen with a 15 ps edge.

**The numbers**

*Readings with a 15 ps edge.*

| Place | As built | With the slot |
|---|---|---|
| The slot, 41 mm from the pins | 91 Ω | 98 Ω |
| Plain line, 28 mm | 91 Ω | 91 Ω |

Plane gap

### A gap in the plane is worse for its size

**Field marks.** A slot 0.5 mm wide across the ground plane, under the bottom-layer pair. The line reads 91 Ω, and the slot 98 Ω.

**Look-alike.** A via with no ground vias makes the same kind of bump. Both are a broken return path.

**Range.** Return current runs right under its trace. It can’t cross the slot, so it goes around, and the detour is inductance. Keep the planes under fast pairs solid.

## Set the edge yourself

*15 to 200 ps, through a fixture or a cable*

The edge decides what the trace can see. Features closer than about one edge apart blur into one: at 50 ps that’s 4.2 mm here.

**Note 16’s explorer: TDR.**

![Note 16’s explorer: TDR](https://nearfieldnotes.com/notes/tdr/fig-explore.png)

*What the figure shows:* The TDR trace of the USB 3 route at the chosen edge. Faster edges show the socket pins and the via pairs as sharp, deep features. Slower ones shrink and blur them. Through a 1 m cable everything reads smoother.

The USB 3 route on the CM5 IO board. Through the fixture at 50 ps, the dashed lines are USB 3.0’s limits for the mated connector, which it sets at that edge.

**The numbers**

*Every edge the control offers. Edges are 20–80%.*

| Edge | Pins, fixture | Vias, fixture | Pins, cable | Vias, cable | Resolution, fixture |
|---|---|---|---|---|---|
| 15 ps | 67 Ω | 96 Ω | 82 Ω | 96 Ω | 1.3 mm |
| 20 ps | 70 Ω | 95 Ω | 83 Ω | 96 Ω | 1.7 mm |
| 25 ps | 73 Ω | 95 Ω | 85 Ω | 96 Ω | 2.1 mm |
| 35 ps | 78 Ω | 94 Ω | 87 Ω | 96 Ω | 3.0 mm |
| 40 ps | 80 Ω | 94 Ω | 88 Ω | 96 Ω | 3.4 mm |
| 50 ps | 83 Ω | 94 Ω | 89 Ω | 96 Ω | 4.2 mm |
| 70 ps | 87 Ω | 93 Ω | 91 Ω | 95 Ω | 5.9 mm |
| 100 ps | 89 Ω | 93 Ω | 92 Ω | 95 Ω | 8.5 mm |
| 131 ps | 90 Ω | 93 Ω | 93 Ω | 95 Ω | 11.1 mm |
| 200 ps | 91 Ω | 92 Ω | 94 Ω | 94 Ω | 16.9 mm |

## Fixtures, not cables

*What sits in front of the board*

Compliance tests put the board on a short fixture, and the cable shows why.

**Fig. 16h: Fixture or cable.**

![Fig. 16h: Fixture or cable](https://nearfieldnotes.com/notes/tdr/fig-16h.png)

*What the figure shows:* Figure 16h: the same route seen with a 15 ps edge through 60 mm of fixture and through a 1 m cable. The socket pins read 67 Ω through the fixture and 82 Ω through the cable.

The same route and the same 15 ps edge, launched at the TDR. The cable is a stand-in: 1.8 dB of loss per meter at 2.5 GHz.

**The numbers**

*A 15 ps edge launched at the TDR.*

| Place | Through the fixture | Through 1 m of cable |
|---|---|---|
| Socket pins | 67 Ω | 82 Ω |
| Hole past the pins | 103 Ω | 97 Ω |
| First via pair | 96 Ω | 96 Ω |
| Second via pair | 95 Ω | 96 Ω |

Cable loss

### A cable slows the edge before it gets there

**Field marks.** Through 1 m of USB cable, the cable’s loss slows the 15 ps edge on the way. The socket pins read 82 Ω instead of 67 Ω.

**Look-alike.** A slower edge from the TDR blurs the trace the same way.

**Range.** A TDR is only as sharp as what sits in front of it. Short fixtures keep the edge.

## What the specs ask for

*Each one names its edge*

Many fast standards check impedance with a TDR, and each one that does fixes the edge. Faster links care about smaller features, so they test with sharper edges.

**Fig. 16i: The edge each test uses.**

![Fig. 16i: The edge each test uses](https://nearfieldnotes.com/notes/tdr/fig-16i.png)

*What the figure shows:* Figure 16i: the edge each standard's TDR test asks for, timed 20 to 80%. USB 2.0, 400 ps. HDMI 1.4 and 2.0, 131 ps, given as 200 ps 10 to 90%. SATA, 70 ps. USB 3.0, 50 ps. DisplayPort 1.2, 50 ps. USB-C, 40 ps. DisplayPort 2.1, 25 ps. PCIe 3.0, 23 ps, given as 35 ps 10 to 90%.

Open dots are given 10–90% in their spec and drawn here at 20–80%.

**The numbers**

*Open dots are converted from a 10–90% edge: for a smooth edge, 10–90% is 1.52 times 20–80%.*

| Standard | What is tested | Edge, 20–80% | As the spec gives it |
|---|---|---|---|
| USB 2.0 | Pair in a USB-C cable | 400 ps | 400 ps |
| HDMI 1.4 and 2.0 | Cable | 131 ps | 200 ps, 10–90% |
| SATA | Cable and connector | 70 ps | 70 ps |
| USB 3.0 | Mated connector | 50 ps | 50 ps |
| DisplayPort 1.2 | Cable | 50 ps | 50 ps |
| USB-C | Mated connector | 40 ps | 40 ps |
| DisplayPort 2.1 | DP80 cable | 25 ps | 25 ps |
| PCIe 3.0 | Board traces | 23 ps | 35 ps, 10–90% |

Spec check

### This route passes USB 3.0 at 50 ps

**Field marks.** USB 3.0 asks for 90 ± 15 Ω on the mated connector, at a 50 ps edge. The whole route reads 83 to 94 Ω.

**Look-alike.** At 25 ps the same socket dips to 73 Ω. That edge belongs to DisplayPort 2.1’s cable test, so USB 3.0’s window says nothing about it.

**Range.** Check how the edge is timed. A 50 ps edge timed 20–80% is about 76 ps timed 10–90%. HDMI and PCIe give theirs 10–90%.

## No TDR? A VNA

*The same echoes, against frequency*

A network analyzer measures the same reflections, one frequency at a time.

**Fig. 16j: Reflection at the port.**

![Fig. 16j: Reflection at the port](https://nearfieldnotes.com/notes/tdr/fig-16j.png)

*What the figure shows:* Figure 16j: the reflection a network analyzer reads at the same port, against frequency: -27 dB at the low end, rising to -5 dB at 20 GHz.

The same route, the same 60 mm fixture and the same 100 Ω reference as the TDR.

**The numbers**

*Reflection at the TDR's port, 100 Ω reference, through 60 mm of fixture.*

| Frequency | Reflection |
|---|---|
| 1 GHz | −24.2 dB |
| 2.5 GHz | −17.3 dB |
| 5 GHz | −18.0 dB |
| 10 GHz | −8.6 dB |
| 15 GHz | −5.8 dB |
| 20 GHz | −5.0 dB |

VNA

### One inverse FFT turns it into a TDR trace

**Field marks.** The reflection climbs from −27 dB at 0.1 GHz to −5 dB at 20 GHz, as the socket and vias start to matter.

**Look-alike.** Every TDR trace of this route comes from reflections like these, shaped by the edge and turned back into time.

**Range.** Most VNAs have a time-domain mode, hobby NanoVNAs included. Less bandwidth means a slower edge, still enough for cables and connectors.

Key to TDR traces

## What is this bump?

1. 1a The trace dips Go to 2
2. 1b The trace climbs Go to 3
3. 2a It comes back to the line Extra capacitance: pads, pins, a stub
4. 2b It steps down and stays A lower-impedance line from there on
5. 2c It drops to zero A short
6. 3a It comes back to the line Extra inductance or a broken return path
7. 3b It steps up and stays A higher-impedance line from there on
8. 3c It shoots off the top An open end

To find where: echo time ÷ 11.8 ps is mm of trace on this board.

#### Conditions

- **Board:** Raspberry Pi CM5 IO board, revision 2, from its KiCad files. 4 layers, 1.6 mm: top, 0.09 mm, ground, 1.28 mm, ground, 0.09 mm, bottom. FR-4, ε_r 4.5.
- **Route:** USB 3 receive pair, 0.147 mm traces with a 0.253 mm gap. 76.45 mm from the socket pins to the module.
- **Lines:** 90.1 Ω and 5.91 ps/mm from a 2D cross-section with solder mask. The HDMI pair is 96.5 Ω.
- **Pieces:** The socket’s footprint, the via pair under the CM5 with and without its ground vias, and the slot, each solved in 3D from the board’s copper. The slot sits 41 mm from the pins, where its window lies on the bottom-layer run.
- **Stand-ins:** Fixture 60 mm at 90 Ω. Cable 1 m at 90 Ω with 1.8 dB/m at 2.5 GHz. Plug and socket contacts 20 mm at 98 Ω. Module 6 mm at 88 Ω into a 90 Ω receiver.
- **TDR:** 100 Ω differential source, a smooth edge, rise times 20–80%
- **Finger:** A 2D cross-section: 0.25 mm of dry skin over tissue, through the mask, pressed flat over 6 mm. It reads 12% low. A 3D solve of a fingertip on the same pair dips 15%.
- **Solver:** openEMS v0.37 for the pieces, chained into the lines in the frequency domain. Copper has skin loss and FR-4 a loss tangent of 0.02.

Simulated only. Nothing on this page has been measured on a board yet.

#### Limits

- The cable, the plug in the socket and the module have no design files. They set the trace left of the pins and past 76 mm.
- Both via pairs use the solve of the one under the CM5. The socket-side pair has its own ground vias and may read a little differently.
- Each piece was driven from one side. Its reflection from the other side is mirrored from the first, which holds for small reflections like these.
- The pieces were solved to 40 GHz. At 40 GHz a 15 ps edge still has 8% of its low-frequency strength, so 15 ps readings are the least sure.

#### Files

- tdrsim/route.py The route, pieced together
- tdrsim/line_fd.py The line solver and the TDR
- runs/field/The 3D pieces
- runs/layout/cm5io.json The board’s copper, read from KiCad
- docs/spec_tdr.md Every spec’s TDR test, with its source

#### Sources

- [Raspberry Pi’s CM5 IO board design files](https://pip.raspberrypi.com/categories/1098-design-files)
- [USB 3.0 specification, mated connector impedance, §5.6.1.2](https://www.usb.org/sites/default/files/usb_30_spec_070113.zip)
- [USB Type-C specification 2.5, §3.7.3.1 and the USB D+/D− cable test](https://usb.org/sites/default/files/USB%20Type-C%202.5%20Release%20202603.zip)
- [Serial ATA revision 3.0](https://sata-io.org/system/files/specifications/SerialATA_Revision_3_0_Gold.pdf)
- [Keysight, DisplayPort 2.1 passive cable test](https://www.keysight.com/content/dam/keysight/en/doc/gate/solution-briefs/DisplayPort-DP-Version-2-1-Passive-Cable-Test-MOI.pdf)
- HDMI 1.4b and 2.0 specifications, cable TDR test
- VESA DisplayPort 1.2 standard, cable TDR test
- PCI Express CEM 3.0, trace impedance test
- [Teledyne LeCroy, rise time and spatial resolution](https://teledynelecroy.com/doc/rise-time-and-spatial-resolution)
- [openEMS, the field solver](https://github.com/thliebig/openEMS)

What should the next note be? [Ask for one](https://nearfieldnotes.com/#ask-for-a-note)

---

Source: https://nearfieldnotes.com/notes/tdr/

Cite as: Michael Walker, “TDR”, Near Field Notes, Note 16, Rev 1, 5 Nov 2026. https://nearfieldnotes.com/notes/tdr/

Figures: free to reuse under CC BY 4.0 (https://nearfieldnotes.com/license/). Each one's image is linked under its name. Credit Michael Walker, Near Field Notes, and link the figure: this address plus #fig- and its number, like https://nearfieldnotes.com/notes/tdr/#fig-16.