Note 14Signal integrity Rev 1 Watch the video · 1:58

PHY and link layer

What does the PHY do, and what does the link layer do?

The PHY decides how bits look on the wire. It sets the voltages, the line code and where the clock comes from. The link layer decides what the bits mean. It marks where a frame starts, who it’s for and whether it arrived intact. Either one can change while the other stays.

HDMI 2.1 shows the split. In its FRL mode, the old clock pair becomes a fourth data lane, and the clock rides inside the data, much as DisplayPort has done since its 2006 spec.

The figure sweeps the four pairs on a Rockchip RK3588 board through the old TMDS mode, then FRL.

HDMI 2.1, before and after FRL

A Rockchip RK3588 driving an Amphenol HDMI receptacle

Drawn one bit per step. The TMDS lanes carry real TMDS code, and its clock completes one cycle for every 10-bit character. FRL’s 16b/18b code isn’t public, so its lanes show scrambled bits. FRL runs each lane at a fixed 3 to 12 Gb/s.

Two layers

Layer 1 and layer 2

Every wired link splits its job in two. The physical layer, or PHY, moves raw bits. It sets the voltages, the line code that turns bits into levels, and how the far end finds the clock. The data link layer above it gathers the bits into frames, addresses them and checks them for errors.

The start of an Ethernet frame shows both. On 10BASE-T, every bit is an edge in the middle of its slot, rising for a 1 and falling for a 0, so the edges carry the clock as well. The link layer then reads 10101011 as the start of a frame.

The two layers

10BASE-T’s Manchester code for the last bits of the preamble, the start frame delimiter and the first bits of an address. Start is the 7-byte preamble and the delimiter.

Ethernet, in two chips

MAC, then PHY

Ethernet often gives each layer a chip of its own. The MAC, the link layer, sits inside the processor and builds each frame. It hands the frame over RGMII to a separate PHY chip, which drives four twisted pairs through the jack’s transformers.

RGMII comes with a classic bring-up bug. Its clock has to arrive 1.5 to 2 ns after its data, and someone has to add that delay. The PHY can add it, or the MAC, or a longer trace.

MAC and PHY

Rendered at the parts’ datasheet sizes, with the traces routed for the picture. RGMII is purple and the four pairs are blue.

One frame, four PHYs

1980 to now

The frame the MAC builds has kept its fields since September 1980. They are the destination, source, type, data and a 32-bit check. The IEEE project for 800 Gb/s Ethernet committed to keeping them.

The PHY under it has been replaced again and again. 10BASE-T sends Manchester code. 100BASE-TX steps between three levels. Gigabit sends five levels on all four pairs, both ways at once, and 10GBASE-T sends sixteen at 800 Mbaud, with error correction on top.

Four Ethernet PHYs

24 symbols of each, so each row runs to its own time scale. 10BASE-T and 100BASE-TX come from the real encoders. The PAM rows stand for scrambled data.

Ethernet

IEEE 802.3

Gigabit needs all four pairs, A to D, but autonegotiation and 100 Mb/s use only A and B. So a cable with a break in pair C or D still agrees on 1 Gb/s, then fails to link.

Downshift

TI’s DP83867 falls back after 4 failed tries by default. Linux then logs that a downshift occurred and asks you to check the cabling.

290

Ethernet

One frame since 1980, under every speed

Field marks. A small square PHY chip near an RJ45 jack, with RGMII on one side and four pairs on the other. The RTL8211F is a 5 mm QFN with 40 pads.

Look-alike. 10BASE-T, hiding in every faster port. Autonegotiation speaks in bursts of its old link pulses, which a 10BASE-T port reads as its own.

Range. 10 Mb/s to 10 Gb/s on twisted pairs, and 800 Gb/s on the same frame. Frames run from 64 to 1518 bytes, or 1522 with a VLAN tag. The CRC-32 came from AUTODIN II, a US military network.

Habitat. Any board with an RJ45 jack. Some gigabit PHYs, such as TI’s DP83867 and Marvell’s 88E1512, can downshift. Not every one can.

291

One PHY, a choice of link layers

Combo PHYs

Some chips turn it around, with one PHY and a choice of link layers on top. Each of the Rockchip RK3568’s three SerDes lanes can be one of two or three interfaces, and the board picks which.

It’s one job per lane. A board that uses lane 2 for PCIe gives up SATA and SGMII on it.

The RK3568’s lanes

From Rockchip’s RK3568 datasheet, as quoted in the review of its Linux driver. Filled: one way a board might set the three lanes.

It works because those PHYs are close cousins. USB 3.0 shares PCIe 2.0’s signaling. Both run at 5 Gb/s, with the same 8b/10b code carrying the clock. Intel’s PIPE spec, begun for PCIe in 2002, now gives one PHY interface for PCIe, SATA, USB, DisplayPort and USB4.

8b/10b turns each byte into one of a set of 10-bit codes, chosen to keep the line balanced and full of edges for the clock. The byte 4Ah becomes 0101010101.

8b/10b

Real 8b/10b from the PHY_link encoder, starting at negative running disparity. 4Ah is the code D10.2.

MIPI CSI-2

One link layer, two PHYs

The reverse happens too, with one link layer on different PHYs. A phone camera’s CSI-2 link can run on a D-PHY, which sends its clock on a lane of its own, or on a C-PHY, which uses three wires per lane at three levels and builds the clock in.

MIPI CSI-2

A C-PHY trio changes state every symbol, so every symbol brings a clock edge. It packs 16 bits into 7 symbols. The module follows the Raspberry Pi Camera Module 3.

292

MIPI CSI-2

A camera link on two kinds of wire

Field marks. A flat ribbon from a camera module to the board, 15 ways wide on the Raspberry Pi Camera Module 3.

Look-alike. D-PHY since version 3.5, which can also build its clock into the data and free its clock lane.

Range. One AMD D-PHY core runs up to four data lanes at 80 to 3200 Mb/s, with a 10 Mb/s low-power mode. C-PHY carries about 2.28 bits per symbol, or 3.56 in its newer mode that packs 32 bits into 9 symbols.

Habitat. Between image sensors and processors in phones, and in cars over A-PHY, up to 15 m.

293

Bluetooth LE

Three PHYs, one link

A radio link can even change PHY while it runs. Bluetooth LE has three. LE 1M is the original. LE 2M is twice as fast, and LE Coded spends 2 or 8 symbols on every bit to reach farther.

Bluetooth LE’s PHYs

Rates and required receiver sensitivities from the Bluetooth Core 5.4 spec. Air time is a byte’s 8 bits at each rate.

294

Bluetooth LE

Three PHYs, switched on a live link

Field marks. Three link-layer messages, LL_PHY_REQ, LL_PHY_RSP and LL_PHY_UPDATE_IND, that move a live connection to a new PHY.

Look-alike. LE 1M and LE Coded share one modulation at 1 Msym/s. Only the coding differs.

Range. 2 Mb/s on LE 2M down to 125 kb/s on LE Coded with S=8, which must hear signals 12 dB weaker than the uncoded PHYs need.

Habitat. Every LE radio. LE 1M is required and LE Coded is optional. LE 2M and LE Coded both arrived in Bluetooth 5.0.

295

CAN

The wire picks who talks

On CAN, the PHY even settles who may talk. A transceiver drives the bus for a 0 and lets it rest for a 1, so when two nodes send at once, the bus shows the 0.

Each node reads the bus back as it sends its ID. One that sends a 1 and reads a 0 has lost, and goes quiet. The lowest ID wins, and its frame carries on untouched.

CAN arbitration

Three nodes start at once. Voltages are the TJA1051’s typical outputs at 5 V. A 0 is called dominant and a 1 recessive.

296

CAN

A bus where 0 always wins

Field marks. An 8-pin transceiver such as NXP’s TJA1051 on two lines, CANH and CANL. Both rest at 2.5 V for a 1 and spread to 3.5 and 1.5 V for a 0.

Look-alike. CAN FD, which fights for the bus the same way at up to 1 Mb/s, then speeds up for the data.

Range. Classic CAN runs at up to 1 Mb/s. The TJA1051 takes CAN FD’s data phase to 5 Mb/s, with up to 64 bytes a frame.

Habitat. Cars and machines. The transceiver is only the analog end of the PHY. The controller does the bit timing and the link layer, and resends a frame after an error by itself.

297

HDMI

DVI with sound

HDMI began as DVI. HDMI 1.0, final in December 2002, kept DVI’s TMDS PHY. That’s three data pairs and a clock pair, each line pulled up to 3.3 V through 50 Ω at the screen. Its link layer added sound, in packets fitted into the gaps between lines and frames.

HDMI’s gaps

Not to scale. The bars stand for any picture.

298

HDMI

DVI’s wires, with sound and packets on top

Field marks. A 19-pin Type A receptacle with its lower corners cut. The Amphenol part in the opening figure is 15 mm wide.

Look-alike. DVI, which shares its TMDS. A wire-only adapter works, and the source just leaves the packets out.

Range. TMDS on three data pairs and a clock. FRL on 3 or 4 lanes at 3 to 12 Gb/s each, 48 Gb/s in all. HDMI 2.2, published in 2025, takes FRL to 96 Gb/s.

Habitat. TVs, monitors, consoles and laptops, and boards like the RK3588’s.

299

DisplayPort

On four kinds of wire

DisplayPort started from a link with no clock wire. It has 1, 2 or 4 lanes that carry the clock in the data, AC-coupled at 400 mV by default, and a slow side channel, AUX, for setup. It has since run on PHYs that aren’t its own.

DisplayPort’s routes

USB4 drops DisplayPort’s stuffing symbols and error-correction parity at one end and rebuilds them at the other. USB-C’s Alt Mode can’t do DP++.

300

DisplayPort

A link layer that rides other PHYs

Field marks. A 20-pin receptacle with one corner cut. The Molex 47272 is 16.1 mm wide.

Look-alike. Thunderbolt 3, whose PHY DisplayPort 2.0 borrowed. VESA later aligned DisplayPort 2.1 with USB4’s PHY.

Range. From 1.62 Gb/s a lane with 8b/10b up to 20 Gb/s with DP 2.0’s 128b/132b. A basic DP++ adapter tops out at 165 MHz, single-link DVI’s limit.

Habitat. PC monitors, laptop panels as eDP, and USB-C and USB4 docks.

301

Back to HDMI 2.1

Lanes alike, wires apart

FRL brought HDMI close to DisplayPort in structure. It has up to four lanes with the clock in the data, a few fixed rates, link training and Reed-Solomon error correction.

Its wires stayed HDMI’s. The sink still pulls each line up to 3.3 V, where DisplayPort couples through capacitors. They are close enough for one PHY to do both. The RK3588’s Samsung-designed PHY drives either HDMI 2.1 at up to 12 Gb/s a lane or a laptop panel’s eDP, picked by its driver each time it powers on.

The wires

Simplified. HDMI’s terminations from the DVI 1.0 spec and TI’s TMDS1204 datasheet, DisplayPort’s swing from VESA. An FRL source may also be AC-coupled if it adds resistors to set HDMI’s levels.

Side by side

Every link on this page

PHYs and link layers

Link	PHY	Code	Rate	Clock
Ethernet	10BASE-T	Manchester	10 Mb/s on 2 pairs	In the data
Ethernet	100BASE-TX	4B5B, then MLT-3	125 Mbaud on 2 pairs	In the data
Ethernet	1000BASE-T	PAM-5	250 Mb/s on each of 4 pairs	In the data
Ethernet	10GBASE-T	PAM-16 with LDPC	800 Mbaud on each of 4 pairs	In the data
USB 3.0	SuperSpeed	8b/10b	5 Gb/s	In the data
PCIe 2.0	Gen 2	8b/10b	5 Gb/s	In the data
MIPI CSI-2	D-PHY	Bits on each lane	Up to 3.2 Gb/s a lane in one core	Its own lane
MIPI CSI-2	C-PHY	16 bits in 7 symbols	About 2.28 bits a symbol	In the data
Bluetooth LE	LE 1M, LE 2M, LE Coded	None, or 2 or 8 symbols a bit	125 kb/s to 2 Mb/s	In the data
CAN	ISO 11898-2	A stuff bit after 5 equal bits	1 Mb/s, CAN FD data to 5 Mb/s	On the edges
HDMI, DVI	TMDS	8 bits to 10	Up to 1.65 Gb/s a pair on one DVI link	Its own pair
HDMI 2.1	FRL	16b/18b	3 to 12 Gb/s on 3 or 4 lanes	In the data
DisplayPort	Main link	8b/10b	1.62, 2.7, 5.4 or 8.1 Gb/s a lane	In the data
DisplayPort 2.x	UHBR	128b/132b	10, 13.5 or 20 Gb/s a lane	In the data
DisplayPort	USB4’s, tunneled	USB4 packets	Shares the USB4 link	USB4’s

Rates are per lane or pair where a link has several. Every entry is sourced below.

Read the two layers apart and the odd cases add up. Ethernet keeps one frame on ever faster PHYs. One PHY serves several link layers. DisplayPort’s link layer rides whichever PHY reaches the screen.

Conditions

Method: No simulation. Each waveform is the bits or symbols that PHY sends, from the PHY_link project’s encoders.
Exact codes: 10BASE-T’s Manchester, 100BASE-TX’s 4B5B, scrambler and MLT-3, DVI’s TMDS, 8b/10b, CAN arbitration and C-PHY’s wire states
Levels only: 1000BASE-T’s PAM-5, 10GBASE-T’s PAM-16 and HDMI’s FRL, as scrambled data
Renders: Blender, with parts at their datasheet sizes: Rockchip RK3588, Amphenol 10029449-111RLF, Realtek RTL8211F, HanRun HR911130A, NXP TJA1051T/3 and a module after the Raspberry Pi Camera Module 3. Traces are routed for the picture.
Claims: Each one checked against its source in the project’s research notes, with datasheet values from NXP, Microchip and the DVI 1.0 spec

Drawn from specs and datasheets. Nothing on this page was measured.

Limits

The waveforms are ideal symbols with smooth edges, not what arrives after a cable.
HDMI’s spec isn’t public. Its packets in the gaps are described from a Sony patent, and FRL from test-equipment and IP vendors.
Downshift is a vendor feature. Realtek’s datasheet doesn’t mention it, though Linux supports it on the RTL8211F.
The RK3588’s combo PHY drives HDMI or eDP. Its external DisplayPort comes from a different PHY.
The D-PHY rates are one vendor’s core, not the spec’s limits.

Files

sim/linecodes.pyThe encoders behind every waveform
render/scene.pyThe renders
refs/research.md57 checked claims and their sources
anim/hook.pyThe video these figures come from

Sources

Like this note?

Rev 1 · 4 Nov 2026

Rev 14 Nov 2026First published

Each fix gets a line here, with the reader's name if they want credit.

Did it answer your question?

Want more on this?

Report a problem

What should the next note be? Ask for one