---
title: "How hard should you drive a half bridge?"
topic: "Gate ringing"
answer: "As hard as it goes without ringing. At its 1 A power-on setting, the gate driver on moteus-c1 rings its 80 V FET to 81 V at 48 V. 190 mA stays at 48 V, and 30 mA loses 3.3 W at 100 kHz."
url: "https://nearfieldnotes.com/notes/gate-ringing/"
site: "Near Field Notes"
author: "Michael Walker"
note: 4
family: "Power"
published: "2026-11-02"
revised: "2026-11-02"
revision: 1
video: "https://nearfieldnotes.com/videos/gate-ringing/"
---

Note 4 · [Power](https://nearfieldnotes.com/families/power/) · Rev 1 · [Watch the video · 0:12](https://nearfieldnotes.com/videos/gate-ringing/)

Gate ringing

# How hard should you drive a half bridge?

**Short answer:** As hard as it goes without ringing. At its 1 A power-on setting, the gate driver on moteus-c1 rings its 80 V FET to 81 V at 48 V. 190 mA stays at 48 V, and 30 mA loses 3.3 W at 100 kHz.

**Note 4’s opening figure: The knob, turning up.** One driver setting a step

![Note 4’s opening figure: The knob, turning up](https://nearfieldnotes.com/notes/gate-ringing/fig-opening.png)

*What the figure shows:* The voltage on moteus-c1's low-side FET after the high side turns on, as the gate current steps from 30 mA to 1 A. 30 mA: 48 V peak, 3.3 W lost. 60 mA: 48 V peak, 1.7 W lost. 120 mA: 48 V peak, 0.86 W lost. 190 mA: 48 V peak, 0.57 W lost. 260 mA: 51 V peak, 0.44 W lost. 330 mA: 57 V peak, 0.37 W lost. 440 mA: 67 V peak, 0.31 W lost. 680 mA: 80 V peak, 0.26 W lost. 1 A: 81 V peak, 0.23 W lost.

Voltage on the low-side FET of moteus-c1 at each DRV8323 gate-current setting. 48 V, 10 A. 0 ns is the high side’s turn-on command.

## The gate drive loops

*Phase A of moteus-c1 r1.2*

One phase of mjbots’ moteus-c1 motor controller. The gate driver U4 turns the high-side FET Q1 on by pushing current into its gate. How hard it pushes, from 10 mA to 1 A, is the knob on this page. Every chart shows the voltage on the low-side FET Q2 as Q1 snaps on.

**Fig. 4: The circuit.**

![Fig. 4: The circuit](https://nearfieldnotes.com/notes/gate-ringing/fig-4.png)

*What the figure shows:* Figure 4: the circuit. A 48 V rail feeds the high-side FET Q1 over the low-side FET Q2. Their middle, the switch node, sends 10 A to the motor through pad A and returns to the driver U4 as SH. U4 drives Q1's gate from GH and Q2's from GL. C19, 0.1 µF, ties the 48 V rail to Q2's source, which runs through the 2 mΩ shunt R6 to ground. Four 4.7 µF capacitors, C42 to C45, tie the rail to ground. Two gate loops are marked. The high side's runs out of U4 on GH to Q1's gate and back from Q1's source on SH. The low side's runs out on GL to Q2's gate and back from Q2's source through R6 and ground to U4. The voltage on the FET is Q2's, drain to source.

U4 drives both gates. Each gate’s current runs out of U4 to the gate and back from that FET’s source. Q2’s voltage, from + to −, is the one in every chart.

**Fig. 4b: On the board.**

![Fig. 4b: On the board](https://nearfieldnotes.com/notes/gate-ringing/fig-4b.png)

*What the figure shows:* Figure 4b: where on the board. The whole moteus-c1, 38 mm square, with phase A boxed at its top edge, next to the driver U4. Beside it, phase A's top copper as the field solver saw it: the high-side FET Q1 on the right, the low-side FET Q2 on the left, C19 below them, the shunt R6 to its left and pad A for the motor above. From the bottom left corner, toward U4, three traces run side by side up between the FETs: GL to Q2's gate, and GH with SH beside it to Q1's gate and source. Those are the copper that carries the gate current in the field solve. The low side's current comes back in the ground plane under GL.

The whole board from the top, and phase A enlarged. The colored traces carry the gate current.

**Fig. 4c: Voltage on the FET.**

![Fig. 4c: Voltage on the FET](https://nearfieldnotes.com/notes/gate-ringing/fig-4c.png)

*What the figure shows:* Figure 4c: the voltage on the low-side FET after the hard edge. At full gate drive, 1 A, it rings to 81 V on an 80 V FET. At the firmware's 60 mA it rises slowly to 48 V.

The low-side FET of moteus-c1 at the driver’s power-on 1 A and at the firmware’s 60 mA. 48 V, 10 A.

Gate ringing

### At full strength the 80 V FET takes 81 V

**Field marks.** The high side slams on and the switch node climbs in under 2 ns. The FET that is off overshoots the 48 V supply to 81 V and rings at 235 MHz.

**Look-alike.** At the firmware’s 60 mA the edge takes 16 ns and stops at 48 V. The ring is the loop’s inductance against the off FET’s [capacitance](https://nearfieldnotes.com/glossary/#g-coss): `f = 1/(2π √(L C))`. This board’s 1.8 nH loop rings at 235 MHz. The same copper without its inner planes, 4.0 nH, rings at 161 MHz.

**Range.** Any half bridge that switches hard. Here 1 A peaks at 81 V, 330 mA at 57 V and 260 mA at 51 V. 190 mA and below stay at 48 V.

**Habitat.** Phase A of mjbots’ moteus-c1 r1.2: two Toshiba TPN19008QM FETs and a TI DRV8323S with no gate resistors, at 48 V and 10 A.

Key to gate drive

## How do you slow the edge?

1. 1a The driver sets its gate current The fastest step that doesn’t ring
2. 1b The driver has one strength Go to 2
3. 2a The resistor that stops the ring lets the gate drain in time That gate resistor
4. 2b It drains so slowly that both FETs conduct Rg_on, with Rg_off and a diode across it

On moteus-c1 at 48 V the fastest step that doesn’t ring is 190 mA, and 120 mA without the inner planes. With a fixed 1.7 A driver, TI’s DRV8302, at 24 V, 33 Ω stops the ring. At 68 Ω both FETs conduct and lose 28 µJ a cycle. 68 Ω with 4.7 Ω and a diode across it loses 5 µJ. A slow gate changes which FET is best, as [Note 20](https://nearfieldnotes.com/notes/fet-choice/) shows.

## Turn the knob yourself

*Every driver setting, on 4 and 2 layers*

**Note 4’s explorer: Voltage on the FET.**

![Note 4’s explorer: Voltage on the FET](https://nearfieldnotes.com/notes/gate-ringing/fig-explore.png)

*What the figure shows:* The voltage on the low-side FET after the high side turns on, at the chosen gate current and board. Faster settings ring past the 48 V supply, and on 2 layers they ring higher from slower settings.

The low-side FET of moteus-c1 at 48 V and 10 A. 2 layers is the same copper field-solved without its inner planes. Lost is the switching loss of both FETs at 100 kHz. Dead time is how long the driver waits for one gate to drain before it opens the other.

**Fig. 4d: What each setting costs.**

![Fig. 4d: What each setting costs](https://nearfieldnotes.com/notes/gate-ringing/fig-4d.png)

*What the figure shows:* Figure 4d: peak voltage on the FET and switching loss at 100 kHz against gate current. As built, the peak stays at 48 V up to 190 mA and climbs to 81 V at 1 A. On 2 layers it reaches 50 V at 120 mA and rings from the next step up. The loss falls from 3.3 W at 30 mA to 0.57 W at 190 mA and 0.23 W at 1 A. Conduction at 10 A costs 1.5 W.

Every DRV8323 step from 30 mA to 1 A at 48 V and 10 A. The loss is as built, both FETs, beyond conduction.

Gate current

### 190 mA is the fastest edge that doesn’t ring

**Field marks.** At 190 mA the FET peaks at 48 V and the two FETs lose 0.57 W switching at 100 kHz.

**Look-alike.** 30 mA is just as clean and loses 3.3 W. That’s more than the 1.5 W the FETs lose carrying 10 A.

**Range.** Above 190 mA each step buys a faster edge and a higher spike. Below it only the loss grows. A slow gate also stretches the [dead time](https://nearfieldnotes.com/glossary/#g-dead-time), 58 ns at 1 A and 261 ns at 30 mA, and the motor current rides the [body diode](https://nearfieldnotes.com/glossary/#g-body-diode) meanwhile. Without the inner planes the ring starts at 140 mA.

#### Conditions

- **Board:** mjbots moteus-c1 r1.2, phase A
- **FETs:** Toshiba TPN19008QM, 80 V, with a model fitted by hand to the datasheet
- **Driver:** TI DRV8323S, modeled from its datasheet’s gate-current steps, with no gate resistors
- **Load:** 48 V, with 10 A leaving the switch node, so the high side switches hard
- **Copper:** Loop and gate inductances from an openEMS solve of all four layers: a 1.83 nH loop as built, 4.03 nH with the inner planes taken out
- **Loss:** The energy both FETs lose in a cycle beyond conduction, times 100 kHz
- **Solver:** ngspice, 48 runs. The driver’s 10 mA step doesn’t finish its edge in the 700 ns on-time, so it isn’t shown.

Simulated only. Nothing on this page has been measured on a board yet.

#### Limits

- 81 V is the FET model’s breakdown. From 680 mA up the peak reads 80 to 81 V because the model avalanches. Without that clamp the ring would go higher.
- The loss in the FET’s capacitance is a guess, 0.3 Ω. At 1 A the peak reads 81 V up to 0.3 Ω, 78 V at 1 Ω and 58 V at 3 Ω.
- A probe on the pins sees the off gate swing from −3.4 to +4.8 V at 1 A. The gate inside the package swings from −0.9 to +1.3 V. Part of what the probe reads is the package’s own inductance.

#### Files

- gatesim/bench.py The half bridge, its driver and the board’s copper
- gatesim/fets.py The FET model and its datasheet check
- fieldsim/model.py The four copper layers, as the field solver saw them

#### Sources

- [moteus-c1’s KiCad files, Apache-2.0](https://github.com/mjbots/moteus/tree/main/hw/c1)
- [TI DRV8323, the gate driver](https://www.ti.com/product/DRV8323)
- [ngspice, the circuit simulator](https://ngspice.sourceforge.io/)
- [openEMS, the field solver](https://github.com/thliebig/openEMS)

What should the next note be? [Ask for one](https://nearfieldnotes.com/#ask-for-a-note)

---

Source: https://nearfieldnotes.com/notes/gate-ringing/

Cite as: Michael Walker, “Gate ringing”, Near Field Notes, Note 4, Rev 1, 2 Nov 2026. https://nearfieldnotes.com/notes/gate-ringing/

Figures: free to reuse under CC BY 4.0 (https://nearfieldnotes.com/license/). Each one's image is linked under its name. Credit Michael Walker, Near Field Notes, and link the figure: this address plus #fig- and its number, like https://nearfieldnotes.com/notes/gate-ringing/#fig-4.