---
title: "How do C-PHY trios carry a camera’s video, and how do they compare with regular CSI?"
topic: "CSI trios"
answer: "A trio drives its three wires to three different levels and changes the pattern every symbol, so its receiver takes the clock from the data and 16 bits ride in every 7 symbols. Regular CSI runs on D-PHY, which sends one bit per symbol on each wire pair and the clock on a pair of its own. At the same 2.5 Gsym/s on 15 cm of flex, a trio carries 5.71 Gb/s on three wires and a D-PHY lane 2.5 Gb/s on two."
url: "https://nearfieldnotes.com/notes/csi-trios/"
site: "Near Field Notes"
author: "Michael Walker"
note: 29
family: "Signal integrity"
published: "2026-11-09"
revised: "2026-11-09"
revision: 1
video: "https://nearfieldnotes.com/videos/csi-trios/"
---

Note 29 · [Signal integrity](https://nearfieldnotes.com/families/si/) · Rev 1 · [Watch the video · 2:42](https://nearfieldnotes.com/videos/csi-trios/)

CSI trios

# How do C-PHY trios carry a camera’s video, and how do they compare with regular CSI?

**Short answer:** A trio drives its three wires to three different levels and changes the pattern every symbol, so its receiver takes the clock from the data and 16 bits ride in every 7 symbols. Regular CSI runs on D-PHY, which sends one bit per symbol on each wire pair and the clock on a pair of its own. At the same 2.5 Gsym/s on 15 cm of flex, a trio carries 5.71 Gb/s on three wires and a D-PHY lane 2.5 Gb/s on two.

The figure sends one 16-bit word both ways. The trio uses the one entry of the spec’s word table that is public, and it is done in 2.8 ns, before the D-PHY lane is halfway through.

**Note 29’s opening figure: One word, two PHYs.**

![Note 29’s opening figure: One word, two PHYs](https://nearfieldnotes.com/notes/csi-trios/fig-opening.png)

*What the figure shows:* Figure: the same 16 bits, the word 0x7290, sent two ways at 2.5 gigasymbols a second and drawn at the far end of 15 cm of flex. On a C-PHY trio they go as seven symbols, 0 2 2 4 1 0 0, and take 2.8 nanoseconds. Its three wires sit at three different levels in every symbol, and its three receivers see one big and two small differences. On a D-PHY lane they go as 16 bits, one per symbol, and take 6.4 nanoseconds, while the clock pair beside it toggles.

**Key**

- A, A−B
- B, B−C
- C, C−A
- D-PHY
- Clock

The word 0x7290 at 2.5 Gsym/s, at the far end of 15 cm of flex. At rest both have sent all 16 bits: the trio as the symbols 0224100 in 2.8 ns, the D-PHY lane in 6.4 ns.

**The numbers**

*The word 0x7290 at 2.5 Gsym/s on each.*

| Lane | Wires | Sent as | Takes |
|---|---|---|---|
| C-PHY trio | 3 | 7 symbols: 0 2 2 4 1 0 0 | 2.8 ns |
| D-PHY lane | 2, and 2 for the clock | 16 bits: 0 1 1 1 0 0 1 0 1 0 0 1 0 0 0 0 | 6.4 ns |

## A camera on a flex

*10 wires, or 9*

A phone camera is an image sensor in a small module. Its pictures leave on a flex, a thin printed cable, for a plug on the main board. CSI-2 is MIPI’s camera protocol: it packs the pixels into packets, and a [PHY](https://nearfieldnotes.com/glossary/#g-phy) underneath turns them into voltages on the wires. [Note 14](https://nearfieldnotes.com/notes/phy-link/) sorts out which job is whose. A car camera can sit meters from its computer, so a serializer carries its CSI-2 data over coax, as [Note 27](https://nearfieldnotes.com/notes/car-camera-coax/) shows.

CSI-2 runs on one of two PHYs. D-PHY, the older one, sends data on wire pairs. MIPI still calls it the predominant PHY for cameras. C-PHY sends data on trios, three wires that work as one lane.

**Fig. 29: A camera module and its flex.**

![Fig. 29: A camera module and its flex](https://nearfieldnotes.com/notes/csi-trios/fig-29.png)

*What the figure shows:* Figure 29: a phone-style camera module, 10 mm square and 6 mm tall, with its lens on top. A thin orange flex leaves its side, bends in an S and runs 15 cm to a small board-to-board plug.

A generic module, drawn for this note. Its flex carries ten signal traces between two grounds, as Fig. 29f shows at the plug.

A D-PHY lane is a differential pair. One wire goes high as the other goes low, and the receiver reads the difference as a bit. The clock rides on a pair of its own, so a 4-lane camera needs 10 wires.

A trio’s three wires each have their own driver. At the far end each meets 50 Ω to one shared point, and three receivers compare the wires in pairs: A with B, B with C and C with A.

**Fig. 29b: One lane of each.**

![Fig. 29b: One lane of each](https://nearfieldnotes.com/notes/csi-trios/fig-29b.png)

*What the figure shows:* Figure 29b: two schematics. A D-PHY lane: one driver with true and inverted outputs P and N, two 50 ohm lines 15 cm long, and at the far end a 50 ohm resistor from each wire to a shared node with 10 pF to ground. One comparator reads P minus N as the bit. A C-PHY trio: three single-ended drivers A, B and C, three 50 ohm lines, and a 50 ohm resistor from each wire to one shared node with 10 pF to ground. Three comparators read A minus B, B minus C and C minus A.

As this note simulates them: 50 Ω drivers, 15 cm of 50 Ω flex and 1 pF on every pad. A D-PHY camera has four such lanes and a clock lane built the same way.

## Three wires, three levels

*Six states*

In every symbol a trio’s three wires sit at three different levels: one high, one low and one in the middle. There are six ways to arrange them, the six wire states, and each symbol moves the trio from one to another.

**Fig. 29c: Six states, five moves.**

![Fig. 29c: Six states, five moves](https://nearfieldnotes.com/notes/csi-trios/fig-29c.png)

*What the figure shows:* Figure 29c: the six wire states on a ring, each drawn as three bars for wires A, B and C. In +x, A is high, B low and C in the middle. Going round: +x, minus z, +y, minus x, +z, minus y. From +x five arrows lead to the other five, each marked with its symbol: 0 to +z, 1 to minus z, 2 to +y, 3 to minus y and 4 to minus x. No arrow stays at +x.

Each bar is a wire’s level. The letter names the pair that sees the big difference, x for A−B, y for B−C and z for C−A, and the sign says which way. The arrows are the five moves out of +x.

**The numbers**

*Wire levels at the far end are about 107, 199 and 294 mV. Receiver voltages are the middle value at the sampling instant over the run. The last five columns are the state each symbol leads to.*

| State | A | B | C | A−B, mV | B−C, mV | C−A, mV | 0 | 1 | 2 | 3 | 4 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| +x | High | Low | Middle | +168 | −84 | −84 | +z | −z | +y | −y | −x |
| −x | Low | High | Middle | −168 | +84 | +84 | −z | +z | −y | +y | +x |
| +y | Middle | High | Low | −84 | +168 | −84 | +x | −x | +z | −z | −y |
| −y | Middle | Low | High | +84 | −168 | +84 | −x | +x | −z | +z | +y |
| +z | Low | Middle | High | −84 | −84 | +168 | +y | −y | +x | −x | −z |
| −z | High | Middle | Low | +84 | +84 | −168 | −y | +y | −x | +x | +z |

Wire states

### One big difference and two small ones

**Field marks.** Each receiver only asks which wire of its pair is higher. The pair holding the high and the low wire sees a strong difference. The other two see half as much, of the opposite sign. In this note’s run, at the sampling instant, strong was 168 mV and weak 84 mV.

**Look-alike.** Three-level symbols such as USB4 version 2.0’s, in [Note 26](https://nearfieldnotes.com/notes/line-codes/). There each symbol’s level is the data. In a trio no wire’s level means anything alone. Only the order of the three does.

**Range.** Keysight puts a trio’s swing near 200 mV peak to peak. Here the wires sat near 107 mV, 199 mV and 294 mV at the far end.

**Habitat.** Every C-PHY trio, in cameras and in displays. Xiaomi’s Pad 5 Pro panel runs over three trios, by its Linux device tree.

## Sixteen bits in seven symbols

*16/7 of the symbol rate*

The state has to change every symbol, so from any state there are five places to go. A symbol is one of those five moves, numbered 0 to 4. Seven symbols give enough patterns for every 16-bit word:

`5^7 = 78,125 ≥ 2^16 = 65,536`

So a trio carries 16 bits in every 7 symbols, and its data rate is

`R_b = R_s × 16/7`

where R_b: data rate of one trio (bit/s); R_s: symbol rate of one trio (symbol/s).

`5.71 Gb/s = 2.5 Gsym/s × 16/7`

A D-PHY lane carries one bit per symbol, 2.5 Gb/s at the same rate.

**Fig. 29d: What a lane and a port carry.**

![Fig. 29d: What a lane and a port carry](https://nearfieldnotes.com/notes/csi-trios/fig-29d.png)

*What the figure shows:* Figure 29d: data rate in gigabits a second, as bars. At 2.5 gigasymbols a second a D-PHY lane carries 2.5 and a trio 5.71. MIPI's 2014 port figures: four lanes and a clock, 10 wires, 10; three trios, 9 wires, 17.1. Sony's IMX06A sensor at its top rates: 18 on four D-PHY lanes, 41.1 on three trios.

The first two bars are this note’s run. Then MIPI’s figures from C-PHY’s launch in 2014, and one Sony sensor at each PHY’s top rate, from its data sheet.

**The numbers**

*A trio carries 16 bits in 7 symbols, so its data rate is 16/7 of its symbol rate.*

|  | Data rate | From |
|---|---|---|
| D-PHY lane, 2 wires | 2.5 Gb/s | This note’s run |
| C-PHY trio, 3 wires | 5.71 Gb/s | This note’s run |
| 4 lanes and a clock, 10 wires | 10 Gb/s | MIPI press release, 2014 |
| 3 trios, 9 wires | 17.1 Gb/s | MIPI press release, 2014 |
| 4 lanes at 4.5 Gb/s | 18 Gb/s | Sony IMX06A data sheet |
| 3 trios at 6 Gsym/s | 41.1 Gb/s | Sony IMX06A data sheet |

Words and symbols

### A table, not a sum

**Field marks.** The spec maps each 16-bit word to 7 symbols through a fixed table. That leaves 12,589 patterns over, and some become control words. Every burst opens with the sync word 3444443, and 4444444 marks its end. The one entry made public is 0x7290, sent as 0224100.

**Look-alike.** A base-5 number. Seven digits from 0 to 4 look like one, but 0x7290 in base 5 is 1414303. This mapping is C-PHY’s [line code](https://nearfieldnotes.com/glossary/#g-line-code), and the spec that holds it is for MIPI members only.

**Range.** MIPI rates C-PHY at up to 6 Gsym/s per trio on a standard channel, 13.7 Gb/s. Version 3.0 adds a mode with 18 states that packs 32 bits into 9 symbols.

**Habitat.** Sony’s IMX06A sensor runs full resolution at 30 frames a second on C-PHY and at 15 on D-PHY, by its data sheet.

## The clock is in the edges

*No clock wires*

Because the state always changes, at least one receiver flips in every symbol. The receiver builds its clock from those flips, so a trio needs no clock wires.

**Fig. 29e: Where the clock comes from.**

![Fig. 29e: Where the clock comes from](https://nearfieldnotes.com/notes/csi-trios/fig-29e.png)

*What the figure shows:* Figure 29e: the opening figure's three receivers for the word's seven symbols, with a dot where each crosses zero. Every symbol flips at least one receiver: symbol 4 flips three, symbols 0 and 2 flip two, symbol 1 flips one. Below, a clock tick sits at the first crossing in each symbol, with a bar after it for the 0.6 symbol the receiver ignores further crossings.

The opening figure’s receivers again, for the seven symbols of 0x7290. Each dot is a receiver crossing zero. A clock tick sits at the first crossing in each symbol, and the bar after it is the 0.6 of a symbol for which this note’s receiver then ignores crossings.

**The numbers**

*Crossings are timed from where the symbol's edge is centered at the receiver.*

| Symbol | Move | Receivers that flip | Their crossings, from the symbol edge |
|---|---|---|---|
| 0 | +x to +z | 2 | −23 ps, 38 ps |
| 2 | +z to +x | 2 | −36 ps, 32 ps |
| 2 | +x to +y | 2 | −28 ps, 36 ps |
| 4 | +y to −y | 3 | −9.9 ps, −4.3 ps, 1.4 ps |
| 1 | −y to +x | 1 | −1.3 ps |
| 0 | +x to +z | 2 | −28 ps, 39 ps |
| 0 | +z to +y | 2 | −28 ps, 28 ps |

Clock recovery

### The first edge wins

**Field marks.** Symbol 4 flips all three receivers. Symbols 0 and 2 flip two, and 1 and 3 flip one. The receiver starts its clock on whichever crosses first, waits a fixed delay, then samples all three.

**Look-alike.** D-PHY’s embedded clock. Since version 3.5, from 2023, a D-PHY lane can drop its clock pair too. It codes its data with 128b/132b, one of the codes in [Note 26](https://nearfieldnotes.com/notes/line-codes/).

**Range.** Which receiver crosses first changes from symbol to symbol, so the clock edges wander. On the 15 cm flex they spread over 47 ps.

**Habitat.** Every C-PHY receiver. Keysight’s and Tektronix’s test tools trigger their eye diagrams on the first crossing for the same reason.

## The same ten pins

*One left over*

Four D-PHY lanes and their clock use 10 pins. Three trios use 9. Chips that speak both put them on the same pins, so one board can take either kind of camera.

Qualcomm’s QCS6490 names one ball CSI0_A0_CLK_M: the D-PHY clock’s minus wire, or wire A of trio 0. Rockchip’s RK3588 names its tenth pin MIPI_DPHY0_RX_D3P/NO_USE. NVIDIA rates its Jetson AGX Orin at 40 Gb/s of camera input as D-PHY and 164 Gb/s as C-PHY, on the same pins.

**Fig. 29f: The plug, two ways.**

![Fig. 29f: The plug, two ways](https://nearfieldnotes.com/notes/csi-trios/fig-29f.png)

*What the figure shows:* Figure 29f: the same 0.35 mm pitch plug twice, its row of twelve pins seen from above. The outer two are ground. As D-PHY the ten between are lit as five pairs: lanes D0 and D1, the clock, lanes D2 and D3. As C-PHY the first nine are lit as three trios, each wired A, B, C, and the tenth is unused.

The plug at the end of Fig. 29’s flex, its twelve pins at 0.35 mm. The pairing follows Synopsys’s pin map. Which pin becomes which wire differs from chip to chip.

**The numbers**

*Pins counted between the two grounds. The pairing is Synopsys’s combo PHY pin map.*

| Pin | As D-PHY | As C-PHY |
|---|---|---|
| 1 | D0P | Trio 0, A |
| 2 | D0N | Trio 0, B |
| 3 | D1P | Trio 0, C |
| 4 | D1N | Trio 1, A |
| 5 | CKP | Trio 1, B |
| 6 | CKN | Trio 1, C |
| 7 | D2P | Trio 2, A |
| 8 | D2N | Trio 2, B |
| 9 | D3P | Trio 2, C |
| 10 | D3N | Unused |

## A smaller eye

*133 mV against 308 mV*

The trio pays for its speed in margin. Its receivers see steps of two sizes, and they cross zero at different times. [Note 8](https://nearfieldnotes.com/notes/eye-diagram/) shows how to read an [eye diagram](https://nearfieldnotes.com/glossary/#g-eye-diagram).

**Fig. 29g: Three eyes.**

![Fig. 29g: Three eyes](https://nearfieldnotes.com/notes/csi-trios/fig-29g.png)

*What the figure shows:* Figure 29g: three eye diagrams, every symbol of the run folded onto two symbol times, drawn as bands where the traces pass. The D-PHY pair on 15 cm of flex crosses zero within 15 ps and opens 308 mV tall. The trio's three receivers on the same flex cross within 76 ps and open 133 mV. On a lossless 5 mm line the trio still crosses within 48 ps, with 175 mV open.

Every symbol of the run, folded onto two symbol times. Darker bands are where more traces pass. The bracket on 0 V spans the crossings, and the bar at the sampling instant is the eye height.

**The numbers**

*Eye height is twice the smallest receiver voltage at the sampling instant; eye width is the symbol time less the crossing spread.*

|  | Crossings spread over | Eye height | Eye width |
|---|---|---|---|
| D-PHY pair, 15 cm | 15 ps | 308 mV | 385 ps |
| Trio, 15 cm | 76 ps | 133 mV | 324 ps |
| Trio, lossless 5 mm | 48 ps | 175 mV | 352 ps |

Encoding jitter

### Crossings that wander on a perfect wire

**Field marks.** When a symbol moves one receiver by a big step and another by a small one, they cross zero at different points of the edge. On the 15 cm flex the trio’s crossings spread over 76 ps, against 15 ps for the D-PHY pair, and its eye is 133 mV tall against 308 mV.

**Look-alike.** [Jitter](https://nearfieldnotes.com/glossary/#g-jitter) from the flex. On a lossless 5 mm line the trio’s crossings still spread over 48 ps. The coding causes it, and loss adds to it.

**Range.** Symbols 0 and 2 spread the most, about 60 ps here. Symbol 4 flips all three receivers almost together, within 10 ps. One receiver flips on 1 and 3, so they have one crossing.

**Habitat.** Fast trios, where it eats into the eye. From version 2.0, C-PHY adds receiver equalization.

## No clock tone

*One tone, or none*

A D-PHY clock pair sends 1010 over and over, so its energy piles into one frequency, half the bit rate. Data spreads its energy across the band. A trio has no clock pair.

**Fig. 29h: What each lane sends, by frequency.**

![Fig. 29h: What each lane sends, by frequency](https://nearfieldnotes.com/notes/csi-trios/fig-29h.png)

*What the figure shows:* Figure 29h: three spectra from 0 to 6 GHz of the voltage across each lane's receiver, in dBmV per 3.125 MHz bin. The D-PHY clock pair is one tall tone, 45.3 dBmV at 1.25 GHz. The D-PHY data pair peaks at 27.9 dBmV and the trio's A minus B at 26.2 dBmV, both spread smoothly across the band.

The voltage across each lane’s receiver at 2.5 Gsym/s, in dBmV, the highest of every four 3.125 MHz bins from 50 MHz up. Bins below 0 dBmV sit on the axis. The clock pair’s tone is 17 dB above the data pair’s highest bin.

**The numbers**

*Common-mode current is the sum of a lane's wire currents, with one wire 5 ps late. Matched, it is below −50 dBµA on all three.*

| Lane | Highest bin, receiver voltage | Highest bin, common-mode current with 5 ps skew |
|---|---|---|
| D-PHY clock pair | 45.3 dBmV at 1.25 GHz | 41.7 dBµA at 1.25 GHz |
| D-PHY data pair | 27.9 dBmV at 0.26 GHz | 20.1 dBµA at 1.28 GHz |
| Trio, A−B | 26.2 dBmV at 0.49 GHz | 19.0 dBµA at 1.29 GHz |

Emissions

### A tone at half the bit rate

**Field marks.** At 2.5 Gb/s the clock pair’s tone stands at 1.25 GHz, 45.3 dBmV. The data pair peaks at 27.9 dBmV and the trio at 26.2 dBmV, spread over hundreds of megahertz. Qualcomm’s 2016 C-PHY talk says its “embedded clock eliminates clock spur emissions”.

**Look-alike.** A balanced pair that can’t radiate. A pair radiates through the current its wires don’t cancel. With one wire 5 ps late, the clock pair’s common-mode current peaked at 41.7 dBµA, against 20.1 dBµA for a data pair and 19.0 dBµA for a trio.

**Range.** D-PHY has fixes of its own. [Spread-spectrum](https://nearfieldnotes.com/glossary/#g-spread-spectrum) clocking came in version 2.0, and CSI-2 version 2.0 added scrambling of the data.

**Habitat.** Phones, where the camera flex runs past the radios. Raspberry Pi warns that Camera Module 3 can interfere with GPS L1 at 1575 MHz, from a harmonic of its CSI clock.

## Routing a trio

*Three pairs at once*

A trio is three pairs at once, A−B, B−C and C−A, and each should be 100 Ω, the [impedance](https://nearfieldnotes.com/glossary/#g-characteristic-impedance) its receivers terminate. Laid side by side like a differential pair, the outer two wires are twice as far apart as the neighbors, and the three pairs drift apart.

**Fig. 29i: Spacing a flex trio.**

![Fig. 29i: Spacing a flex trio](https://nearfieldnotes.com/notes/csi-trios/fig-29i.png)

*What the figure shows:* Figure 29i: two cross-sections of three flex traces over a ground plane, half a trace width apart and 2.5 widths apart, and a chart of each pair's impedance against the gap. Half a width apart, the neighboring pairs A−B and B−C are 80 and 80 ohms and the outer pair C−A 94. All three approach 100 ohms as the gap grows, within 2 ohms of it by 2.5 widths, the spacing AMD's guide asks for.

A 2D field solve of three traces on a flex, one pair at a time. The vertical line is AMD’s rule for spacing inside a trio, 2.5 trace widths.

**The numbers**

*Traces 96 µm wide and 12 µm thick on 50 µm of polyimide over a ground plane, under 25 µm of coverlay.*

| Gap, widths | Gap, µm | A−B, Ω | B−C, Ω | C−A, Ω |
|---|---|---|---|---|
| 0.5 | 48 | 79.8 | 80.4 | 94.2 |
| 1 | 96 | 90.6 | 91.3 | 98.4 |
| 2 | 192 | 97.1 | 97.9 | 100.0 |
| 2.5 | 240 | 98.3 | 99.1 | 100.2 |
| 3 | 288 | 99.0 | 99.8 | 100.3 |
| 4 | 384 | 99.7 | 100.5 | 100.4 |

Layout

### Space it, and keep it even

**Field marks.** Half a width apart, A−B and B−C fall to 80 Ω and 80 Ω while C−A stays at 94 Ω. At 2.5 widths all three are within 2 Ω of 100. AMD’s Versal guide asks for that spacing, 5 widths to the next trio and ±2 ps of skew inside a trio.

**Look-alike.** Routing a trio like a tight differential pair. Coupled tightly, the trio’s crossings spread over 89 ps and its eye fell to 106 mV, against 82 ps and 129 mV at 3 widths.

**Range.** Trios can differ from each other more: AMD allows 160 ps between trios. A Qualcomm patent evens out a flat trio’s outer pair by stacking the wires in a triangle across two layers.

**Habitat.** Any C-PHY board. Linux’s device tree can say in which order a board wired A, B and C, so a layout can swap them.

## Who uses which

*Most flagships offer both*

Flagship phone sensors from Samsung, Sony and OmniVision offer both PHYs on the same pins, and the phone maker picks. Many processors have D-PHY alone, and even a combo port needs a driver that runs it as C-PHY.

**Figure: Sensors.**

Fig. 29j

| Sensor | D-PHY | C-PHY | Source |
|---|---|---|---|
| Sony IMX06A | 4 lanes, 4.5 Gb/s each | 3 trios, 6.0 Gsym/s each | [Data sheet](https://images.nuernbergmesse.de/files/54682dde-4186-6331-80e7-500d123a880d.pdf) |
| Sony LYTIA 901 | 4 lanes, 2.5 Gb/s | 3 trios, 6.0 Gsym/s | [News release](https://www.sony-semicon.com/en/info/2025/2025112701.html) |
| Samsung ISOCELL HP3 | 4 lanes, 2.5 Gb/s | 3 trios, 4.0 Gsym/s | [Product page, archived](http://web.archive.org/web/20240103173556/https://semiconductor.samsung.com/image-sensor/mobile-image-sensor/isocell-hp3/) |
| Samsung ISOCELL GN2 | 4 lanes, 6.5 Gb/s | 3 trios, 3.5 Gsym/s | [Product page](https://semiconductor.samsung.com/image-sensor/mobile-image-sensor/isocell-gn2/) |
| Samsung ISOCELL JN1 | 4 lanes, 2.15 Gb/s | None listed | [Product page, archived](http://web.archive.org/web/20231201130855/https://semiconductor.samsung.com/image-sensor/mobile-image-sensor/isocell-jn1/) |
| OmniVision OV50H | 4 lanes, 3.0 Gb/s | 3 trios, 3.5 Gsym/s | [Product page](https://www.ovt.com/products/ov50h) |
| Raspberry Pi Camera Module 3 | 2 lanes | None | [Linux driver, imx708.c](https://github.com/raspberrypi/linux/tree/rpi-6.18.y/drivers/media/i2c) |

Rates as each maker states them, at each PHY’s top. A trio’s data rate is 16/7 of its symbol rate, so Samsung’s GN2 is the faster on D-PHY: 26 against 24.0 Gb/s.

**Figure: Processors.**

Fig. 29k

| Processor | D-PHY | C-PHY | Source |
|---|---|---|---|
| NVIDIA Jetson AGX Orin | 16 lanes, 40 Gb/s in all | 16 trios, 164 Gb/s in all | [Data sheet](https://openzeka.com/wp-content/uploads/2022/03/DS-10662-001_v1.0.pdf) |
| NVIDIA Jetson Orin NX and Orin Nano | 8 lanes | None | [Product page](https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-orin/) |
| Qualcomm QCS6490 | 4-lane ports | 3-trio ports, on the same balls | [Data sheet](https://dl.radxa.com/dragon/q6a/hw/datasheets/80-23889-1_REV_AW_QCS6490_and_QCS5430_Data_Sheet.pdf) |
| Rockchip RK3588 | Six 4-lane ports | Two of them, 3 trios at 2.5 Gsym/s | [Data sheet](https://www.rockchip.fr/RK3588%20datasheet%20V0.1.pdf) |
| MediaTek MT8395 | Three 4-lane ports | In the hardware, not in its ISP driver | [Data sheet](https://static.chipdip.ru/lib/757/DOC028757554.pdf), [Genio docs](https://genio.mediatek.com/doc/android/hw/mt8395-soc.html) |
| Raspberry Pi 5 | Two 4-lane ports | None | [RP1 data sheet](https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf) |

Camera inputs as each maker lists them. On the RK3588 two of the six ports are combo PHYs and four are D-PHY only.

## Which PHY does my camera use?

*Start at the sensor*

The key starts at the sensor, because most offer both and a few offer one.

Key to camera PHYs

### D-PHY, C-PHY or either?

1. 1a The sensor offers one PHY. Its pins name lanes and a clock, D0P and CKN, or trios, A0, B0 and C0 The one it offers
2. 1b It offers both, on the same pins Go to 2
3. 2a The processor’s camera port is D-PHY only, as on a Raspberry Pi or a Jetson Orin NX D-PHY
4. 2b The port is a combo PHY Go to 3
5. 3a Its driver runs the port only as D-PHY D-PHY
6. 3b Its driver runs C-PHY Go to 4
7. 4a The sensor’s D-PHY lanes reach the frame rate you need Either
8. 4b Only its trios do C-PHY

At 4, check the rates rather than assume. Sony’s IMX06A doubles its full-resolution frame rate on C-PHY, but Samsung’s GN2 is faster on D-PHY.

## Step a trio yourself

*6 states, 5 symbols*

Pick a state and a symbol. The ring shows the move, and the waves are that move taken from the simulated run, with a dot where each receiver crosses zero.

**Note 29’s explorer: One symbol.**

![Note 29’s explorer: One symbol](https://nearfieldnotes.com/notes/csi-trios/fig-explore.png)

*What the figure shows:* A ring of the six wire states with an arrow from the chosen state to the one the chosen symbol leads to. Beside it, that one symbol from the simulated run: the three wire voltages, and the three receiver voltages with a dot where each crosses zero. Receivers that don't flip are drawn faint.

**Key**

- A, A−B
- B, B−C
- C, C−A

The waves start 300 ps before the symbol’s edge, the dashed line. Each is the symbol with the middle spread among all of its kind in the run. Receivers that don’t flip are drawn faint.

**The numbers**

*Each drawing is the symbol with the middle spread among all of its kind in the 1,071-symbol run.*

| From | Symbol | To | Receivers that flip | Spread, drawn | Spread, all in the run | Times in the run |
|---|---|---|---|---|---|---|
| +x | 0 | +z | 2 | 61 ps | 56 ps to 70 ps | 38 |
| +x | 1 | −z | 1 | — | — | 37 |
| +x | 2 | +y | 2 | 59 ps | 54 ps to 68 ps | 37 |
| +x | 3 | −y | 1 | — | — | 39 |
| +x | 4 | −x | 3 | 8.9 ps | 1.1 ps to 16 ps | 18 |
| −x | 0 | −z | 2 | 61 ps | 55 ps to 66 ps | 31 |
| −x | 1 | +z | 1 | — | — | 36 |
| −x | 2 | −y | 2 | 62 ps | 54 ps to 69 ps | 32 |
| −x | 3 | +y | 1 | — | — | 44 |
| −x | 4 | +x | 3 | 5.2 ps | 0.1 ps to 18 ps | 33 |
| +y | 0 | +x | 2 | 61 ps | 53 ps to 68 ps | 34 |
| +y | 1 | −x | 1 | — | — | 47 |
| +y | 2 | +z | 2 | 60 ps | 56 ps to 69 ps | 35 |
| +y | 3 | −z | 1 | — | — | 36 |
| +y | 4 | −y | 3 | 5.9 ps | 0.0 ps to 17 ps | 25 |
| −y | 0 | −x | 2 | 62 ps | 54 ps to 69 ps | 48 |
| −y | 1 | +x | 1 | — | — | 26 |
| −y | 2 | −z | 2 | 61 ps | 56 ps to 66 ps | 31 |
| −y | 3 | +z | 1 | — | — | 37 |
| −y | 4 | +y | 3 | 5.9 ps | 0.0 ps to 16 ps | 28 |
| +z | 0 | +y | 2 | 60 ps | 55 ps to 67 ps | 34 |
| +z | 1 | −y | 1 | — | — | 41 |
| +z | 2 | +x | 2 | 62 ps | 55 ps to 68 ps | 43 |
| +z | 3 | −x | 1 | — | — | 29 |
| +z | 4 | −z | 3 | 5.5 ps | 0.0 ps to 19 ps | 32 |
| −z | 0 | −y | 2 | 61 ps | 56 ps to 70 ps | 33 |
| −z | 1 | +y | 1 | — | — | 33 |
| −z | 2 | −x | 2 | 62 ps | 55 ps to 68 ps | 34 |
| −z | 3 | +x | 1 | — | — | 33 |
| −z | 4 | +z | 3 | 5.4 ps | 0.2 ps to 15 ps | 34 |

#### Conditions

- **Method:** Circuit simulation in ngspice of one trio and one D-PHY lane, read by a model receiver. A 2D field solve of the trio’s cross-section. Renders in Blender.
- **Flex:** 15 cm of 50 Ω microstrip, 0.11 mm wide on 50 µm polyimide, effective permittivity 2.7, loss tangent 0.006, with skin loss: 1.7 dB at 1.25 GHz and 2.5 dB at 2.5 GHz.
- **Drivers:** 2.5 Gsym/s, edges half a symbol long, 0.4 V open circuit through 50 Ω, 1 pF on every pad at both ends. Trio levels 0, 0.2 and 0.4 V before the line.
- **Terminations:** C-PHY: 50 Ω from each wire to one node with 10 pF to ground. D-PHY: 50 Ω from each wire to a center tap with 10 pF.
- **The run:** 1,071 symbols on each lane: seven 3s, the sync word, 0x7290 as 0224100, then 150 random words, all decoded. The spec’s table isn’t public, so the random words go through a base-5 stand-in. It changes which moves come up, not what each move looks like. The D-PHY lane carries random bits.
- **Receiver:** The trio’s clock starts at the first crossing in each symbol, samples half a symbol later and ignores crossings for 0.6 of a symbol. The D-PHY lane is sampled mid-bit.
- **Opening figure:** A second D-PHY run carries 0x7290’s 16 bits, most significant first, and a clock pair carries 1010. The clock is drawn half a symbol late, so its edges fall mid-bit.
- **Spectra:** 800 symbols each of a trio with random symbols, a pair with random bits and a clock pair, in 3.125 MHz bins. Common-mode current with one wire 5 ps late.
- **Cross-section:** Fig. 29i and the tight and loose runs use a field-solved trio in place of the flex above: 96 µm traces 12 µm thick on 50 µm polyimide over a ground plane, under 25 µm of coverlay, effective permittivity 2.92. Tight is 0.5 widths apart and loose is 3.

The module and flex are drawn for the picture, not taken from a product.

#### Limits

- The C-PHY and D-PHY specs are for MIPI members and weren’t read. Levels, terminations and layout rules here come from vendors’ documents and patents.
- No equalization, no crosstalk between lanes and no package models.
- The spectra are voltage at the receiver and common-mode current, not radiated field.
- Which PHY a given phone wires up is rarely public.

#### Files

- sim/cphy.py Wire states, moves, receivers and the stand-in mapping
- sim/link.py The trio and the D-PHY lane on 15 cm of flex, and the eyes
- sim/site.py 0x7290 and the clock on a D-PHY lane
- sim/trio3.py Spectra, skew, and tight against loose routing
- sim/xsec3.py The cross-section’s field solve
- render/module.py The module, flex and plug
- refs/research_tech.md How C-PHY and D-PHY signal, with sources
- refs/research_use.md Which sensors and processors use which
- refs/research_routing_emi.md Layout rules and emissions

#### Sources

- [MIPI Alliance, C-PHY specification page](https://www.mipi.org/specifications/c-phy)
- [MIPI Alliance, D-PHY specification page](https://www.mipi.org/specifications/d-phy)
- [MIPI Alliance, C-PHY versions and adoption dates](https://www.mipi.org/hubfs/Specification-Feature-Tables/MIPI-C-PHY-v3.0-Version-History-Table.pdf)
- [MIPI Alliance, MIPI Alliance Introduces MIPI C-PHY Specification, 17 September 2014, reprinted](https://us.design-reuse.com/news/35444/mipi-c-phy-d-phy-m-phy-specifications.html)
- [MIPI Alliance, Embedded Clock Option in D-PHY v3.5, 11 April 2024](https://www.mipi.org/blog/embedded-clock-option-in-d-phy-v3-5-further-expands-specification-appeal)
- [MIPI Alliance, CSI-2 version 2.0 press release, April 2017, reprinted](https://www.businesswirechina.com/en/news/34854.html)
- [M. Hafed, Introspect Technology, MIPI C-PHY and How It Enables Next Generation Display and Camera Implementations, MIPI DevCon 2017: wire states, symbols, the 16-bit mapping and 0x7290](https://www.mipi.org/hubfs/Bangalore-Introspect-C-PHY-and-How-It-Enables-Next-Gen-Display-1.pdf)
- [MIPI DevCon 2022, PHY Roadmap](https://www.mipi.org/hubfs/DevCon-2022/2022-MIPI-DevCon-PHY-Roadmap.pdf)
- [L. Sousa, Synopsys, Why an Integrated MIPI C-PHY/D-PHY IP is Essential, MIPI DevCon 2020: the shared pin map](https://mipi.org/hubfs/DevCon%202020/MIPI-DevCon-2020-Why-an-Integrated-MIPI-C-PHY-D-PHY-IP-is-Essential.pdf)
- [G. Wiley, Qualcomm, Implementing MIPI C-PHY, MIPI DevCon 2016](https://www.slideshare.net/slideshow/mipi-devcon-2016-implementing-mipi-cphy/66405781)
- [X. Jiang, Keysight, Conquer MIPI C-PHY Simulation Challenge, IBIS Summit, November 2025](https://ibis.org/summits/nov25a/jiang.pdf)
- [Tektronix, TekExpress MIPI C-PHY transmitter test application data sheet, 2021, distributor copy](https://netes.com.tr/dosya/tekexpress-mipi-c-phy-transmitter-test-application-cphy20-6-cmcphy20-datasheet)
- [P. Raju and S. Kumar, Tektronix, MIPI D-PHY Physical Layer Test and Measurement Challenges, MIPI DevCon 2016](https://www.slideshare.net/slideshow/mipi-devcon-2016-mipi-dphy-physical-layer-test-measurement-challenges/66404878)
- [Rohde & Schwarz 1SL410, MIPI D-PHY: Debugging and Compliance Testing, December 2023](https://scdn.rohde-schwarz.com/ur/pws/dl_downloads/dl_application/application_notes/1sl410/1SL410_0e_MIPI_D-PHY_debugging_and_compliance_testing.pdf)
- [AMD UG863, Versal Adaptive SoC PCB Design User Guide, MIPI C-PHY, rev. 1.12](https://docs.amd.com/r/en-US/ug863-versal-pcb-design/MIPI-C-PHY)
- [US 8,064,535, Qualcomm, Three phase and polarity encoded serial interface](https://patents.google.com/patent/US8064535)
- [US 9,319,218, Qualcomm, Multi-wire signaling with matched propagation delay among wire pairs](https://patents.google.com/patent/US9319218B2/en)
- [Linux, media: dt-bindings: Add property to describe CSI-2 C-PHY line orders, 2024](https://github.com/torvalds/linux/commit/91a7088096a4)
- [Linux, Xiaomi Pad 5 Pro panel on C-PHY, 2023](https://github.com/torvalds/linux/commit/51c4c2bd6f314de8b1bb7b5c949d2432be19d419)
- [Raspberry Pi documentation, camera pinouts and Camera Module 3](https://github.com/raspberrypi/documentation/tree/master/documentation/asciidoc/accessories/camera)
- [Sony IMX06A-AJ1R-J data sheet, Ver. 1.0](https://images.nuernbergmesse.de/files/54682dde-4186-6331-80e7-500d123a880d.pdf)
- [Qualcomm QCS6490 and QCS5430 data sheet, Rev. AW: ball names](https://dl.radxa.com/dragon/q6a/hw/datasheets/80-23889-1_REV_AW_QCS6490_and_QCS5430_Data_Sheet.pdf)
- [Rockchip RK3588 data sheet, Rev. 0.1: pin names](https://www.rockchip.fr/RK3588%20datasheet%20V0.1.pdf)
- [NVIDIA Jetson AGX Orin Series data sheet, DS-10662-001 v1.0, mirror](https://openzeka.com/wp-content/uploads/2022/03/DS-10662-001_v1.0.pdf)

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Source: https://nearfieldnotes.com/notes/csi-trios/

Cite as: Michael Walker, “CSI trios”, Near Field Notes, Note 29, Rev 1, 9 Nov 2026. https://nearfieldnotes.com/notes/csi-trios/

Figures: free to reuse under CC BY 4.0 (https://nearfieldnotes.com/license/). Each one's image is linked under its name. Credit Michael Walker, Near Field Notes, and link the figure: this address plus #fig- and its number, like https://nearfieldnotes.com/notes/csi-trios/#fig-29.