---
title: "Glossary of circuit board terms"
url: "https://nearfieldnotes.com/glossary/"
site: "Near Field Notes"
---

Glossary

# Words the notes use

**Short answer:** Each word gets a picture, the word it gets mixed up with and the notes that use it.

## A

### Alt mode

Alternate mode, on USB-C

A way for a USB-C port to carry something besides USB, such as DisplayPort video, mostly on its fast pairs and sideband pins. No pin changes job until both ends agree on the mode in messages on CC.

- **Often confused with:** **USB4**. USB4 also runs on all four fast pairs as one link, like Thunderbolt 3. The host enters it with a Power Delivery message of its own, Enter_USB, where an alt mode needs Enter Mode.
- **In notes:** [Note 14, PHY and link layer](https://nearfieldnotes.com/notes/phy-link/) · [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* The 24 pins of a USB-C receptacle as two rows of 12, the A face over the B face turned over, in DisplayPort on 2 lanes. DisplayPort video takes TX2 and RX2, USB 3 keeps TX1 and RX1, USB 2 keeps D+ and D−, DisplayPort's AUX takes both SBU pins and CC1 carries the messages. The arrow points at a DisplayPort pair.

DisplayPort on 2 lanes, Note 23’s rest frame: DP on TX2 and RX2, USB 3 on TX1 and RX1, AUX on both SBU pins. The B face is drawn turned over.

### Antipad

The ring of bare board cleared around a via or pin where it passes through a plane it must not touch.

- **Often confused with:** Thermal relief. An antipad keeps a pin off the plane. A relief joins them through spokes.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/)

*What the figure shows:* A via through a ground plane, top view, with a ring of bare board between them. The arrow points at the ring.

A via through a ground plane, top view. Drawing, not to scale.

## B

### Body diode

Its reverse recovery charge, Qrr, in nC

A diode built into every silicon MOSFET, from source to drain, that carries current backwards through the switch while it’s off. Conducting fills it with charge, and the other switch has to pull that charge out at full voltage, its reverse recovery.

- **Often confused with:** Output capacitance. Both are charge the turning-on switch has to pull out. Every switch holds output charge, GaN too. Only a diode that has conducted holds recovery charge.
- **In notes:** [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 10, Zero-voltage switching](https://nearfieldnotes.com/notes/zvs/) · [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* Note 11's leg at 400 V: current through the top switch as it turns on, with 5 A running backward through the bottom one. With silicon it climbs to 49 A while the bottom switch's body diode empties. With GaN it peaks at 15 A. The arrow points at silicon's.

Note 11’s leg at 400 V, with 5 A running backwards through the bottom switch as the top one turns on. Emptying silicon’s body diode takes 2,336 nC, and the top switch’s current climbs to 49 A. GaN has no body diode, and its current peaks at 15 A.

### Buck converter

A switching converter that makes a lower voltage from a higher one, chopping its input with switches and smoothing it through an inductor and capacitor. Its output sits near its input times its duty cycle.

`V_out ≈ d V_in`

- **Often confused with:** **Buck-boost**. A buck-boost can make its output above or below its input. Note 22’s SIMO runs its 3.3 V rail in buck-boost, so it holds as the cell runs down below 3.3 V.
- **In notes:** [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/) · [Note 10, Zero-voltage switching](https://nearfieldnotes.com/notes/zvs/) · [Note 12, Power inductors](https://nearfieldnotes.com/notes/inductor-types/) · [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* Note 12's buck converter, 12 V to 3.3 V: two switches take turns connecting a 4.7 µH inductor to 12 V or to ground, and the inductor feeds the 3.3 V output and its capacitor. The arrow points at the inductor.

Note 12’s buck, making 3.3 V from 12 V. Two switches take turns connecting its 4.7 µH inductor to 12 V or to ground. Drawing, not to scale.

## C

### CC pins

Configuration channel: CC1 and CC2

Two USB-C pins, CC1 and CC2, that tell a port which way a plug went in and carry the messages that agree on a mode. The plug’s one CC wire meets only one of them, and a device normally pulls it down through Rd, 5.1 kΩ.

- **Often confused with:** SBU pins. The SBU pins, A8 and B8, sit on the other side of the USB 2 pins from CC. They carry nothing in plain USB, while the CC pins say which mode a port is in.
- **In notes:** [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* A port's two CC pins and a device, drawn as a circuit. The plug's CC wire runs from the port's CC1 to the device, which pulls it down to ground through Rd, 5.1 kΩ. Nothing meets CC2. Turned over, the wire would meet CC2 instead. The arrow points at CC1.

The plug the usual way up, its CC wire on CC1, as Note 23 draws every port. Drawing, not to scale.

### CC-CV charging

Constant current, then constant voltage

Charging at a constant current until the cell reaches its full voltage, then holding that voltage while the current tapers off. The charge stops once the current falls to a set fraction, a tenth in Note 15 and a twentieth in Note 18.

- **Often confused with:** Balance charge. A balance charge runs the same CC-CV on the whole pack and also watches every cell. A plain CC-CV charge sees only the pack's total.
- **In notes:** [Note 15, Battery balance](https://nearfieldnotes.com/notes/battery-balance/) · [Note 18, LiPo vs LiFePO4](https://nearfieldnotes.com/notes/lipo-vs-life/) · [Note 21, Power quadrants](https://nearfieldnotes.com/notes/power-quadrants/)

*What the figure shows:* Note 18's LiPo cell charged at 1C from 10%. The current holds at 1C while the voltage climbs to 4.20 V at 48 min. Then the voltage holds at 4.20 V for 31 min while the current tapers to a twentieth. The arrow points at the switch from one to the other.

Note 18's LiPo cell, charged at 1C from 10%. It reaches 4.20 V at 48 min, then holds it for 31 min while the current tapers to a twentieth.

### Cell balancing

Evening out the charge in each cell of a series pack, so every cell ends a charge at its full voltage. A balancer reads each cell through the balance lead and bleeds or moves charge from the one that leads.

- **Often confused with:** **Active balancing**. Most balancers are passive and bleed the leading cell's extra charge through a resistor as heat. Active balancing moves that charge into the other cells instead.
- **In notes:** [Note 13, Capacitors](https://nearfieldnotes.com/notes/capacitor-types/) · [Note 15, Battery balance](https://nearfieldnotes.com/notes/battery-balance/) · [Note 18, LiPo vs LiFePO4](https://nearfieldnotes.com/notes/lipo-vs-life/)

*What the figure shows:* Note 15's 3S pack at the end of two charges. Plain, cells 1 and 2 end at 4.17 V and cell 3 at 4.25 V. Balanced, all three end at 4.20 V. Both packs read 12.60 V. The arrow points at cell 3 on the plain charge.

Note 15's 3S LiPo pack with cell 3 faded to 90%, charged at 2.2 A. Both charges stop at 12.60 V. The plain charge leaves cell 3 at 4.25 V and the others at 4.17 V. A 300 mA bleed brings all three to 4.20 V.

### Characteristic impedance

Z₀, in Ω

The impedance an edge sees as it runs along a line, set by the trace's width, its height over the plane and the board between them. USB 3 pairs are built to 90 Ω, HDMI and DisplayPort pairs to 100 Ω.

`Z _0 = √(L/C)`

- **Often confused with:** **Resistance**. An ohmmeter reads almost nothing along a 90 Ω trace. The 90 Ω comes from the trace's inductance and capacitance, and only a fast edge sees it.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/) · [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/) · [Note 16, TDR](https://nearfieldnotes.com/notes/tdr/)

*What the figure shows:* The CM5 IO board's USB 3 pair cut across, to scale: two traces 0.147 mm wide and 0.253 mm apart, 0.09 mm above the ground plane, under solder mask. Together they make a 90.1 Ω pair. The arrow points at the FR-4 between a trace and the plane.

The CM5 IO board's USB 3 pair, cut across, to scale. Note 16's 2D solve gives 90.1 Ω.

### Coulomb counting

Tracking a battery's charge by adding up the current that flows in and out of it, read through a shunt. Any offset in the current reading adds up too, so the count needs a fixed point to reset it, such as a full charge.

`q = ∫ I d t`

- **Often confused with:** **Voltage gauge**. A voltage gauge reads charge from a rested cell's voltage. On a LiPo it comes close. On a LiFe, 10 mV off fits anything from 42 to 71%.
- **In notes:** [Note 18, LiPo vs LiFePO4](https://nearfieldnotes.com/notes/lipo-vs-life/)

*What the figure shows:* Note 18's LiFe cell charged at 1C from 10%. The current holds at 1C, then tapers in the last minutes. The count is its running total, climbing in a straight line to 2.07 Ah after 56 min. The arrow points at the count.

A123's 26650 LiFe cell from Note 18, charged at 1C from 10%. The count is the running total of the current, 2.07 Ah by the end.

### Current-sense amplifier

An amplifier made to read the few millivolts across a shunt and scale them up for an ADC. Its inputs sit wherever the shunt sits: near ground below the bottom FET, at the supply above the top one.

- **Often confused with:** **Current-sense resistor**. The resistor, or shunt, carries the current and drops a few millivolts. The amp only reads that drop, through two sense lines.
- **In notes:** [Note 5, Shunt taps](https://nearfieldnotes.com/notes/shunt-taps/) · [Note 9, Chip journeys](https://nearfieldnotes.com/notes/chip-journeys/) · [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/)

*What the figure shows:* A shunt in a thick current path carrying 10 A. Thin lines from its two ends run to an amplifier with a gain of 20, whose output goes to the ADC. The arrow points at the amplifier.

moteus-c1's phase A at 10 A. Its 2 mΩ shunt drops 20 mV, and the DRV8323's amp scales that up 20 times. Drawing, not to scale.

## D

### dBµV

Decibels above one microvolt, the unit EMI receivers read in. 0 dBµV is 1 µV, 60 dBµV is 1 mV and 120 dBµV is 1 V.

`dBµV = 20 log _10 (V / 1 µV)`

- **Often confused with:** **dBm**. dBm is power above one milliwatt. Into 50 Ω, 0 dBm is 107 dBµV.
- **In notes:** [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/)

*What the figure shows:* A scale from 0 to 120 dBµV: 0 dBµV is 1 µV, 60 dBµV is 1 mV and 120 dBµV is 1 V.

Every 20 dB is ten times the voltage.

### DC bias

Of a ceramic capacitor

The fall in a ceramic capacitor’s capacitance as the DC voltage across it rises. Its ceramic adds capacitance by turning its dipoles to line up, and once most have turned, each extra volt stores less.

- **Often confused with:** **X5R and X7R**. Codes like X5R and X7R say how capacitance moves with temperature. They say nothing about voltage, and DC bias comes on top.
- **In notes:** [Note 13, Capacitors](https://nearfieldnotes.com/notes/capacitor-types/) · [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* Note 13's Murata MLCC, marked 22 µF: its capacitance against the DC voltage across it, 14.6 µF at 3.3 V and 1.8 µF at its rated 25 V. The arrow points at the 25 V end.

Note 13’s Murata GRM21BR61E226ME44L, marked 22 µF and rated 25 V, from Murata’s SimSurfing data. It holds 14.6 µF at 3.3 V and 1.8 µF at 25 V.

### Dead time

The short gap in a half bridge when both switches are off, so one has let go before the other turns on. The current keeps flowing meanwhile, through a body diode or the switches’ capacitance.

- **Often confused with:** **Turn-on delay**. A turn-on delay is the FET’s own wait after its gate command before any current flows, 886 ns for Note 20’s IRFS7530 at 60 mA. Dead time is the gap a driver leaves between two gate commands.
- **In notes:** [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 10, Zero-voltage switching](https://nearfieldnotes.com/notes/zvs/) · [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/) · [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* The two gate commands in Note 10's switching cell. The upper switch's goes off at 0 ns and the lower switch's comes on at 50 ns, so for 50 ns both are off. The arrow points at that gap.

The two gate commands in Note 10’s switching cell, to scale. The upper switch lets go at 0 ns and the lower one turns on 50 ns later.

### Duty cycle

A share of each cycle, in %

The share of each switching cycle that a switch spends on. In a half bridge it is the share of time the switch node sits at the supply.

`d = t_on/T`

- **Often confused with:** **PWM frequency**. Frequency is how many cycles run each second, 30 kHz on moteus-c1. Duty is how much of each one the switch is on, and either can change without the other.
- **In notes:** [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/) · [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* Phase A as moteus-c1 tells it to switch at 65% duty: at 48 V for 65% of each 33.3 µs cycle, at 0 V for the rest. The arrow points at the time it is on.

Phase A of moteus-c1 as it is told to switch at 65% duty and 30 kHz, drawn with instant edges. It sits at 48 V for 65% of each 33.3 µs cycle.

## E

### EMC

Electromagnetic compatibility

A device's ability to work among other electronics: it keeps its own noise under the limits and survives the noise and zaps around it.

- **Often confused with:** **EMI**. EMI is the noise itself. EMC is passing both ways.
- **In notes:** [Note 2, USB-C shell](https://nearfieldnotes.com/notes/usb-c-shell/) · [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/)

*What the figure shows:* A device sends noise out, its emissions, and takes noise and zaps in, its immunity. EMC is passing both.

Emissions go out, immunity is what a device takes in.

### ESD

Electrostatic discharge, tested in kV to IEC 61000-4-2

A spark from a charged person or object into a device. The current peaks in under a nanosecond.

- **Often confused with:** **Surge**. A surge, tested to IEC 61000-4-5, lasts tens of microseconds and carries far more energy.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/) · [Note 2, USB-C shell](https://nearfieldnotes.com/notes/usb-c-shell/)

*What the figure shows:* ESD current at 8 kV contact, IEC 61000-4-2: 30 A peak in 0.8 ns, 16 A at 30 ns, 8 A at 60 ns.

IEC 61000-4-2 contact discharge at 8 kV, from the standard's current model. It sets 30 A at the peak, 16 A at 30 ns and 8 A at 60 ns.

### Eye diagram

A fast signal cut into slices two bits wide and stacked on top of each other. The opening in the middle is the link's margin: its height in volts, its width in time.

- **Often confused with:** **Eye mask**. The eye is the signal itself. A mask is the keep-out a spec draws inside it, and every sample that lands in the mask is a hit.
- **In notes:** [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/) · [Note 17, Via stubs](https://nearfieldnotes.com/notes/via-stubs/)

*What the figure shows:* Note 8's eye after 12 cm of FR-4: a million bits stacked two bits wide. The opening in the middle is 300 mV tall and 77 ps wide, in a 97 ps bit. The arrow points into the opening.

Note 8's 10.3 Gbit/s lane after 12 cm of FR-4, with jitter and noise, 10⁶ bits. It is 300 mV tall and 77 ps wide in a 97 ps bit.

## G

### GaN FET

Gallium nitride transistor

A power transistor made of gallium nitride instead of silicon. GaN holds its voltage across about a tenth of the distance, so a switch of the same resistance is a smaller chip, with less charge on its gate and drain.

- **Often confused with:** **Silicon carbide**. Silicon carbide is the other material replacing silicon in power switches. SiC FETs are built like silicon ones, body diode included, and serve mostly higher voltages and powers.
- **In notes:** [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/)

*What the figure shows:* The shortest stretch of each material that holds 650 V: 22 µm of silicon, 2.0 µm of GaN. The arrow points at GaN's.

From Note 11: silicon breaks down past about 30 V per µm and GaN past 330 V per µm. With the field spread evenly, that is the shortest stretch of each that holds 650 V.

### Gate charge

Qg, in nC

The charge a driver has to push into a FET’s gate to turn it fully on. At a set gate current, a gate that holds more charge takes longer to fill, and the FET spends longer half on.

`t_g = Q_g/I_g`

- **Often confused with:** **Input capacitance**. Input capacitance, Ciss, is the gate’s capacitance at one voltage, 13.0 nF for Note 20’s IRFS7530. Gate charge also counts the flat stretch, where the gate waits for the drain.
- **In notes:** [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* The gate voltage of Note 11's IPD65R190C7 against the charge put into it, from its datasheet. It climbs, holds flat at 5.4 V while the drain falls, then climbs to 12 V at 27 nC. The arrow points at that end.

Note 11’s 650 V silicon switch, the IPD65R190C7, from its datasheet: about 27 nC brings its gate to 12 V. Along the flat stretch the drain falls while the gate waits.

## H

### Half bridge

Two switches stacked across a supply. The point between them, the switch node, swings from ground to the supply each cycle.

- **Often confused with:** **Full bridge**. A full bridge is two half bridges, with the load between their switch nodes.
- **In notes:** [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* Two switches in series across 48 V, high side over low side. The arrow points at the switch node between them.

One leg of Note 4's 48 V motor drive. The arrow points at the switch node.

## J

### Jitter

In ps, or in UI, a share of one bit

Edges arriving a little early or late against where they belong. Random jitter has no limit, so the more bits you watch, the wider the crossings of an eye get.

- **Often confused with:** **Noise**. Noise moves the signal up and down and thickens the rails. Jitter moves the edges early or late and widens the crossings.
- **In notes:** [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/)

*What the figure shows:* Note 8's eyes 1 and 5 side by side. Both are the same 3 cm lane. Eye 5 has more random jitter, so the crossings where its edges meet spread wide while its rails stay thin. The arrow points at eye 5's crossing.

Note 8's eyes 1 and 5, 10⁶ bits each. Both are the same 3 cm lane. Eye 5 has more random jitter, so its crossings spread while its rails stay thin.

## K

### Kelvin connection

Four-terminal sense

Sense lines that leave a resistor at its body, apart from the current path, so they read the resistor and none of the copper.

- **Often confused with:** **Two-wire sense**. Taps on the current path read the copper's drop too. On Note 5's 0.5 mΩ shunt, taps 2 mm out read 41% high.
- **In notes:** [Note 5, Shunt taps](https://nearfieldnotes.com/notes/shunt-taps/)

*What the figure shows:* A shunt in a thick current path, with two thin sense lines leaving its body and running to an amplifier. The arrow points at one tap.

The thick line carries the current. The thin sense lines carry almost none. Drawing, not to scale.

## L

### LDO

Low-dropout regulator

A linear regulator that needs only a small margin, its dropout, between input and output to hold its output steady. It drops the whole difference across itself and turns it into heat.

`P_heat = (V_in − V_out) · I_out`

- **Often confused with:** **Quiescent current**. Quiescent current is what an LDO draws to run itself, 25 nA for Note 22’s TPS7A02. Its real loss there is the 2.6 V it drops at 40 mA, 104 mW.
- **In notes:** [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* Two of Note 22's LDOs on a 3.7 V cell, as columns of voltage. The 1.1 V rail at 40 mA puts out 44 mW and burns 104 mW in the 2.6 V it drops. The 3.3 V rail at 10 mA drops 0.4 V and burns 4 mW. The arrow points at the 1.1 V rail's drop.

Note 22’s TPS7A02 LDOs on a 3.7 V cell. The 1.1 V rail delivers 44 mW and burns 104 mW doing it. The 3.3 V rail sits close under the cell and loses only 4 mW.

### Lead time

How long a maker or distributor expects a new order of a part to take to arrive. It includes waiting for a factory slot as well as making and shipping.

- **Often confused with:** **Cycle time**. Cycle time is how long a part takes to make and ship. Most of the L298N's 52 weeks is waiting for a slot, not making.
- **In notes:** [Note 9, Chip journeys](https://nearfieldnotes.com/notes/chip-journeys/)

*What the figure shows:* ST's L298N: about 45 to 98 days to make and ship, against a factory lead time of 52 weeks, 364 days. The arrow points at the lead time.

ST's L298N, as Note 9 follows it: about 45 to 98 days from wafer start to the shelf, against a 52-week factory lead time on 26 Oct 2026. Dark is the low estimate, light runs to the high one.

### LiFePO4

Lithium iron phosphate, also LiFe or LFP

A lithium-ion cell with a lithium iron phosphate cathode, full at 3.60 V and averaging 3.3 V. Its voltage barely moves through most of its charge, so voltage says little about how full it is.

- **Often confused with:** **LiPo**. A LiPo has a lithium cobalt oxide cathode, full at 4.20 V and averaging 3.7 V. Hobby packs of both look alike, but a LiFe's label says LiFe and 3.3 V a cell.
- **In notes:** [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/) · [Note 15, Battery balance](https://nearfieldnotes.com/notes/battery-balance/) · [Note 18, LiPo vs LiFePO4](https://nearfieldnotes.com/notes/lipo-vs-life/)

*What the figure shows:* Note 18's two cells, voltage at rest against charge. The LiPo climbs from 3.0 V to 4.2 V the whole way. The LiFe climbs from 2.0 V, then sits near 3.3 V, 3.17 V at 20% and 3.31 V at 80%, before 3.6 V full. The arrow points at the LiFe's flat middle.

Note 18's two cell models at rest. Between the dots, 20 and 80%, the LiPo climbs 299 mV and the LiFe 141 mV, from 3.17 V to 3.31 V.

### Line code

8b/10b, 128b/132b, Manchester and more

The rule that turns bits into the levels a wire carries. Codes like 8b/10b also add bits, so the line stays balanced and full of edges for the receiver's clock.

- **Often confused with:** **Error correction**. Error correction such as Reed-Solomon or LDPC adds bits so the far end can repair errors. A line code adds bits to keep the line balanced and full of edges.
- **In notes:** [Note 14, PHY and link layer](https://nearfieldnotes.com/notes/phy-link/) · [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* The byte 4Ah, 01001010, as eight bits, and below it as its 8b/10b code, 0101010101, in the same time. The code has five 1s and five 0s and changes every bit. The arrow points at the code.

Note 14's byte 4Ah, 01001010, and its 8b/10b code, 0101010101, from Note 14's 8b/10b encoder. The code has five 1s and five 0s.

### Low-side sensing

Measuring current with a shunt between the bottom FET and ground, so the amp's inputs sit near ground. In a half bridge the shunt carries the motor's current only while the bottom FET is on.

- **Often confused with:** **High-side and in-line sensing**. A high-side shunt sits between the supply and the top FET, and an in-line one in the motor's lead. Both need an amp whose inputs ride 48 V.
- **In notes:** [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/)

*What the figure shows:* One leg of a half bridge across 48 V, with a shunt between the bottom switch and ground and an amp reading it. The arrow points at the shunt.

One phase of moteus-c1, which senses low side with a 2 mΩ shunt under each bottom FET. Drawing, not to scale.

## M

### Matching network

A few inductors and capacitors between a radio and its antenna that turn the antenna's impedance into 50 Ω, so less power reflects.

- **Often confused with:** Radiation efficiency. A match only stops reflection. On 10 mm of ground a perfect match lifts 22% to 43%. The rest heats the board.
- **In notes:** [Note 3, Antenna ground](https://nearfieldnotes.com/notes/antenna-ground/)

*What the figure shows:* A radio feeding an antenna through a series inductor and a shunt capacitor, an L-network.

The simplest match, an L-network. Values depend on the antenna.

### Mutual inductance

M, in nH

How much of one circuit’s magnetic field another circuit’s loop catches, per amp. A changing current in the first puts a voltage on the second.

`V = M dI/dt`

- **Often confused with:** **Self-inductance**. Self-inductance, the 4.7 µH printed on an inductor, links a part’s changing current to the voltage across itself. Mutual inductance links it to the voltage on another circuit.
- **In notes:** [Note 12, Power inductors](https://nearfieldnotes.com/notes/inductor-types/)

*What the figure shows:* Note 12's open drum inductor cut through its middle, its right half, with its simulated field lines looping out over the board. A trace runs 1 mm from the part, its ground plane just below. Some lines pass between the trace and the plane, which couples them: 4.03 nH. The arrow points at that strip.

Note 12’s open drum, the Sumida CD43, cut through its middle, with its field lines from Elmer. The lines that pass between the trace and the plane couple the two through 4.03 nH, so 1.85 A every µs puts 7.5 mV on the trace.

## O

### On-resistance

Rds(on), in mΩ

The resistance between a FET’s drain and source while its gate holds it fully on. The current through it heats it by I²R, and the resistance rises as the FET warms.

`P = I^2 R`

- **Often confused with:** **ESR**. ESR is the resistance inside a capacitor, always in series with it. On-resistance belongs to a switch, and only while its gate holds it on.
- **In notes:** [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* A FET with its gate on, drain at the top and source at the bottom, drawn equal to a resistor of 15 mΩ between the same two points. The arrow points at the resistor.

Note 20’s TPN19008QM is 15 mΩ with 10 V on its gate at 25 °C. At 100 °C it is 19.1 mΩ, and 10 A through it makes 1.91 W of heat. Drawing, not to scale.

### Open-circuit voltage

OCV, in V

A cell's voltage with no current flowing, once it has settled. It follows the cell's charge, so a gauge can read charge from it where the curve is steep.

- **Often confused with:** **Voltage under load**. Under load a cell reads below its open-circuit voltage, by its current times its resistance, and above it while charging. TI's gauge waits 30 minutes by default before it trusts the voltage.
- **In notes:** [Note 15, Battery balance](https://nearfieldnotes.com/notes/battery-balance/) · [Note 18, LiPo vs LiFePO4](https://nearfieldnotes.com/notes/lipo-vs-life/)

*What the figure shows:* Note 15's LiPo cell, its voltage against its charge. At rest it climbs from 3.64 V at 10% to 4.2 V full. Giving 10 A it reads 60 mV lower at every charge. The arrow points at the voltage at rest.

Note 15's LiPo cell model, at rest and giving 10 A in flight. Under load it reads 60 mV lower at the same charge, the drop across the 4 mΩ and 2 mΩ the model gives each cell.

### Output capacitance

Coss, in pF. Its charge, Qoss, in nC

The capacitance between a FET’s drain and source, charged whenever voltage builds across the switch. It is largest near zero volts and falls as the voltage rises, so Note 10 counts its charge instead.

`Q_oss = ∫_0^V C_oss dV`

- **Often confused with:** **Eoss**. Eoss is the energy the capacitance stores, 0.65 µJ for Note 10’s two switches at 48 V. Moving their charge costs ½QV, 0.80 µJ, whatever the curve.
- **In notes:** [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 10, Zero-voltage switching](https://nearfieldnotes.com/notes/zvs/) · [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/)

*What the figure shows:* Note 10's TPN19008QM: the capacitance across it against the voltage across it, from 783 pF at 1 V to 227 pF at 48 V. The arrow points at the high end, near zero volts.

Note 10’s TPN19008QM, from its fitted model: 783 pF at 1 V and 227 pF at 48 V. Added up over every volt, it holds 16.7 nC at 48 V.

## P

### PHY

Physical layer, layer 1

The part of a link that decides how bits look on the wire: the voltages, the line code and where the clock comes from. On Ethernet it is often a chip of its own, between the processor and the jack.

- **Often confused with:** **MAC**. The MAC is the link layer. It builds frames, addresses them and checks them. The PHY under it turns their bits into signals on the wire.
- **In notes:** [Note 14, PHY and link layer](https://nearfieldnotes.com/notes/phy-link/)

*What the figure shows:* Ethernet in Note 14 as three blocks. The MAC, the link layer inside the RK3588, builds and checks frames. It hands them over RGMII to the PHY, an RTL8211F, which sets the voltages, the line code and the clock, and sends five levels on each of four pairs to the jack. The arrow points at the PHY.

Note 14's gigabit Ethernet: the MAC hands frames to the PHY over RGMII, and the PHY drives four pairs. Drawing, not to scale.

## Q

### Quadrant

On the voltage-current plane, numbered 1 to 4

One of the four parts of the voltage-current plane, set by the signs of a supply’s output voltage and current. Note 21 puts voltage along the bottom and counts counterclockwise from the top right, so quadrants 1 and 3 source and 2 and 4 sink.

- **Often confused with:** **Keysight’s numbering**. Keysight’s guides put voltage up the side, so their quadrant 2 is Note 21’s quadrant 4, a sink at positive voltage. Source and sink mean the same in both.
- **In notes:** [Note 21, Power quadrants](https://nearfieldnotes.com/notes/power-quadrants/)

*What the figure shows:* The voltage-current plane as Note 21 numbers it: voltage across the output along the bottom, current out up the side. Quadrant 1 is top right and the numbers run counterclockwise. Quadrants 1 and 3 are sources, giving power; quadrants 2 and 4 are sinks, taking power. The arrow points at quadrant 1, where the count starts.

Note 21’s numbering, with voltage along the bottom as in Keithley’s 2460 datasheet. A 1-quadrant supply reaches quadrant 1, a 2-quadrant one adds 4, and a 4-quadrant one reaches all four. Drawing, not to scale.

### Quasi-peak

QP, read in dBµV

An EMI receiver's detector that charges fast and leaks away slowly. Below 30 MHz it charges in 1 ms and leaks over 160 ms, so a signal that repeats often reads near its peak.

- **Often confused with:** **Peak and average**. For the same signal, peak reads highest, then quasi-peak, then average. Note 6 reads all three.
- **In notes:** [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/)

*What the figure shows:* Bursts 0.2 ms long, 100 a second, at 100% of their peak. The quasi-peak detector climbs to 75% and the average is 2%.

Simulated with Note 6's receiver settings. 0.2 ms bursts, 100 a second, read 2.6 dB below their peak on quasi-peak and 34 dB below on average.

## R

### Radiation efficiency

The share of the power an antenna accepts that leaves as radio waves. The rest heats the copper and the board.

`η = P_rad/P_acc`

- **Often confused with:** **Total efficiency**. Total efficiency counts the reflected power too. Note 3's 22% is total, its 43% is radiation efficiency.
- **In notes:** [Note 3, Antenna ground](https://nearfieldnotes.com/notes/antenna-ground/)

*What the figure shows:* Note 3's antenna on 10 mm of ground: 22% of the radio's power radiates, 29% heats the board and 49% reflects.

Note 3's antenna on 10 mm of ground. 22% of the radio's power radiates. Of the 51% the antenna accepts, 43% radiates, its radiation efficiency.

### Read window

The time the bottom FET must stay on in each PWM cycle so a low-side shunt can be read after its amp settles. moteus-c1 needs 3 µs of each 30 kHz cycle, which caps phase duty at 91%.

`d_max = 1 − t_w/T`

- **Often confused with:** **Settling time**. Settling time is how long moteus gives the amp after the bottom FET is told on, 1.5 µs at a gain of 20. It reads in the middle of the window, so the window is twice that.
- **In notes:** [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/)

*What the figure shows:* moteus-c1's low-side shunt over one 33.3 µs cycle at 91% duty. It reads 0 A, then carries the motor's 10 A for 3.1 µs while the bottom FET is on for 3 µs, its read window. The arrow points at that pulse.

moteus-c1's low-side shunt over one 30 kHz cycle at 91% duty, the most a 3 µs window allows. It carries the motor's 10 A for only 3.1 µs of the 33.3 µs.

### Reflection

Reflection coefficient ρ, from −1 to +1

The part of a signal sent back where a line's impedance changes. Its share is the reflection coefficient, from −1 at a short through 0 on a match to +1 at an open end.

`ρ = (Z − Z_0)/(Z + Z_0)`

- **Often confused with:** **Return loss**. Return loss is the same reflection in dB, counted as a loss. A reflection coefficient of 0.1 is 20 dB of return loss.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/) · [Note 3, Antenna ground](https://nearfieldnotes.com/notes/antenna-ground/) · [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/) · [Note 16, TDR](https://nearfieldnotes.com/notes/tdr/) · [Note 17, Via stubs](https://nearfieldnotes.com/notes/via-stubs/)

*What the figure shows:* Reflection coefficient against a 100 Ω source, for any impedance from 0 to 300 Ω. A short sends back −1, 100 Ω sends back nothing, and higher impedances send back a positive share. Note 16's 67 Ω socket pins send back −0.198. The arrow points at them.

Against Note 16's 100 Ω TDR, the 67 Ω socket pins send back −0.198 of the step, so its trace dips.

### Regenerative supply

A supply that sinks through switching stages and returns the power it takes to the grid, instead of turning it into heat.

- **Often confused with:** **Regenerative braking**. Regenerative braking is a motor turning its motion back into current, as Note 21’s braking motor does. A regenerative supply can take that current and pass the power on to the grid.
- **In notes:** [Note 21, Power quadrants](https://nearfieldnotes.com/notes/power-quadrants/)

*What the figure shows:* Two supplies sinking 100 W from a load. A linear stage turns it into heat. A regenerative supply passes it on to the grid. The arrow points at the grid.

Sinking Note 21’s 5 A at 20 V, 100 W. A linear stage turns it into heat, and a regenerative supply returns it to the grid. Drawing, not to scale.

### Ringing

A decaying swing after a fast edge, set by the loop's stray inductance and the FET's capacitance.

`f = 1/(2π√(L C))`

- **Often confused with:** **Overshoot**. Overshoot is the first peak past where the edge settles. Ringing is the whole swing that follows.
- **In notes:** [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/) · [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/) · [Note 20, FET choice](https://nearfieldnotes.com/notes/fet-choice/)

*What the figure shows:* Note 4's switch node at full gate drive: it rings up to 81 V on an 80 V FET, at 236 MHz, and settles at 48 V.

Note 4 at full gate drive: 81 V on an 80 V FET, ringing at 236 MHz. Simulated in SPICE.

### Rise time

Timed 20 to 80% or 10 to 90%, in ps or ns

The time an edge takes to climb from a low share of its step to a high one, usually 20 to 80% or 10 to 90%. On a smooth edge, 10 to 90% is 1.52 times 20 to 80%.

- **Often confused with:** **Slew rate**. Slew rate is how steep the edge is, in V/ns. Rise time is how long it takes, so a bigger step in the same rise time slews faster.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/) · [Note 4, Gate ringing](https://nearfieldnotes.com/notes/gate-ringing/) · [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/) · [Note 16, TDR](https://nearfieldnotes.com/notes/tdr/) · [Note 19, Sense position](https://nearfieldnotes.com/notes/sense-position/)

*What the figure shows:* One smooth edge rising from 0 to 100% of its step. It takes 50 ps from 20 to 80% and 76 ps from 10 to 90%. The arrow points at the edge.

The smooth edge Note 16's TDR sends, at USB 3.0's 50 ps from 20 to 80%. Timed 10 to 90%, the same edge is about 76 ps.

## S

### S21

Insertion loss, in dB

How much of a sine at each frequency gets through a part, from its first port to its second, in dB. 0 dB is all of it, and the more negative, the less gets through.

`S21 = 20 log _10 (V_2 / V_1)`

- **Often confused with:** Reflection. S21 is what gets through to the far end. Reflection, S11, is what comes back toward the source.
- **In notes:** [Note 17, Via stubs](https://nearfieldnotes.com/notes/via-stubs/)

*What the figure shows:* S21 of Note 17's via with its 0.94 mm stub, from 0 to 60 GHz. It stays near 0 dB at low frequencies, falls into a notch at 37.4 GHz where almost nothing gets through, and climbs back above it. The arrow points at the notch.

Note 17's via with its 0.94 mm stub, from its line model. The model has no loss, so the notch at 37.4 GHz has no floor. It is cut off at −30 dB.

### SBU pins

Sideband use: SBU1 and SBU2

Two USB-C pins, SBU1 and SBU2, that carry nothing in plain USB and are free for an alt mode or accessory to use. DisplayPort moves its AUX channel there, and an audio adapter its microphone.

- **Often confused with:** **Sideband channel**. The sideband channel is one signal on the SBU pins, the one Thunderbolt 3 and USB4 run there: SBTX on SBU1 and SBRX on SBU2 in USB4. Other modes put other signals there, such as DisplayPort’s AUX.
- **In notes:** [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* The middle of a USB-C receptacle's A face, A4 to A9: VBUS, CC1, D+, D−, SBU1 and VBUS, with SBU1 dark. The arrow points at it. Below, what the modes put on SBU1 and SBU2: plain USB nothing, DisplayPort its AUX channel, Thunderbolt 3 and USB4 a sideband channel, HDMI its HEAC lines, analog audio the mic and audio ground, the Chromebook debug cable a debug USB link and Apple a serial port.

The middle of Note 23’s A face, A4 to A9, looking into the port. SBU2 sits in the same place on the B face. VirtualLink and the Switch 2 also put DisplayPort’s AUX there.

### SIMO converter

Single-inductor multiple-output converter

A switching converter that feeds several rails from one inductor, filling it and emptying it into one rail at a time. Each rail asks for a packet when it sags, and the rails take turns.

- **Often confused with:** **One buck and LDOs**. One buck followed by LDOs also gets by with one inductor, but each LDO burns its drop as heat. A SIMO switches every rail.
- **In notes:** [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* The SIMO's power stage, drawn simply: a 3.7 V cell, a switch, one 1.5 µH inductor with a switch to ground at each end, then a switch to each of three rails, 1.1, 1.8 and 3.3 V. The arrow points at the one inductor.

Note 22’s MAX77654 on a 3.7 V cell. One 1.5 µH inductor feeds the 1.1, 1.8 and 3.3 V rails through a switch to each. Output capacitors left out. Drawing, not to scale.

### Sink

Of a supply, as against source

A supply sinks when it takes power back from its load instead of giving it. Its voltage and the current out of its + terminal then have opposite signs, so their product is negative.

`P = V I`

- **Often confused with:** **Sink device**. In HDMI, as in Note 14, the sink is the device at the receiving end of a link, such as a display. A supply sinks when power flows back into it.
- **In notes:** [Note 21, Power quadrants](https://nearfieldnotes.com/notes/power-quadrants/)

*What the figure shows:* Note 21's motor braked from 3,000 rpm on a 24 V supply that sinks up to 6 A: the current out of the supply against time. At the brake it turns to −5.2 A, flowing back in, then climbs back through zero as the motor slows. The arrow points at the current flowing back in.

Note 21’s motor braking from 3,000 rpm on a 24 V supply that sinks up to 6 A. The supply takes all 5.2 A the motor sends back and holds the bus at 24.05 V. Near the stop the windings lose more than the motor returns, so the current turns positive.

### SMU

Source-measure unit

A 4-quadrant supply with a precision meter built in, so it can set a voltage and read the current, or set a current and read the voltage. Keithley calls its SMUs SourceMeters.

- **Often confused with:** **Bench supply**. A bench supply shows its voltage and current too, but it only sources, in quadrant 1. An SMU reaches all four quadrants and reads them with a precision meter, which is part of its price.
- **In notes:** [Note 21, Power quadrants](https://nearfieldnotes.com/notes/power-quadrants/)

*What the figure shows:* Note 21's SMU sweeping the ANYSOLAR KXOB25-14X1F solar cell from −1 V to +1 V, limited to 100 mA: current out against the voltage it sets. The curve runs through quadrant 3, below 0 V, then quadrant 4, where the cell makes power, then quadrant 1 above 0.69 V. The arrow points at the stretch below 0 V, reverse bias.

Note 21’s SMU sweeping a KXOB25-14X1F solar cell in sunlight from −1 V to +1 V, limited to 100 mA. It sets each voltage and reads the current through quadrants 3, 4 and 1. The arrow points at reverse bias, below 0 V, which takes a 4-quadrant supply.

### Spread spectrum

Δf, in kHz

Moving a converter's switching frequency in a pattern, so its noise spreads across a band instead of piling up at one frequency.

- **Often confused with:** **Frequency hopping**. Frequency hopping moves a radio's carrier between channels. A converter spreads its own noise to lower the peaks.
- **In notes:** [Note 6, Spread spectrum](https://nearfieldnotes.com/notes/spread-spectrum/)

*What the figure shows:* Note 6's switching frequency, cycle by cycle: a triangle of ±11.4 kHz plus a jump each cycle, about 15 kHz either side of 400 kHz.

TI's pattern for the LM62460, as Note 6 models it.

### Supercapacitor

Supercap, in farads

A capacitor that stores charge as ions packed against porous carbon, with no insulating layer. The carbon’s huge surface lets a small can hold a whole farad, at only a few volts.

- **Often confused with:** **Lithium-ion capacitor**. A lithium-ion capacitor is half supercap, half battery. Note 13’s runs 1 mW for 40 h against the supercap’s 52 min, but must never go below 2.2 V.
- **In notes:** [Note 13, Capacitors](https://nearfieldnotes.com/notes/capacitor-types/)

*What the figure shows:* A supercapacitor cut open, charged. Two sheets of carbon stand in a liquid full of ions, with a separator between them. Negative ions pack against the positive sheet and positive ions against the negative one. The arrow points at one packed layer.

Charged, negative ions gather at the positive carbon and positive ions at the negative one. Note 13’s 1 F supercap, rated 2.7 V, runs 1 mW for 52 min. Drawing, not to scale.

### SuperSpeed pair

TX1, RX1, TX2 and RX2

One of the four fast pairs of pins in a USB-C receptacle, TX1, RX1, TX2 and RX2, that carry USB 3 or an alt mode’s fast signals. Plain USB 3 uses one TX and one RX pair, picked by which way the plug went in.

- **Often confused with:** **Lane**. A USB 3 lane is two pairs, one TX and one RX. A DisplayPort lane is one pair, so DisplayPort on 2 lanes takes TX2 and RX2.
- **In notes:** [Note 1, Ground cut](https://nearfieldnotes.com/notes/ground-cut/) · [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* The 24 pins of a USB-C receptacle as two rows of 12, the A face over the B face turned over. The four SuperSpeed pairs are dark, each a + and a − contact: TX1 and RX2 at the two ends of the A face, TX2 and RX1 at the ends of the B face. With the plug the usual way up, USB 3 uses TX1 and RX1. Turned over, it uses TX2 and RX2. The arrow points at TX1.

Note 23’s 24 pins, looking into the port, with the B face turned over so B1 sits where A1 does. Each pair is a + and a − contact.

## T

### TDR

Time-domain reflectometry

A step source and a fast scope on one line, which read the line's impedance from the echoes of a step. Each echo's delay says where the impedance changes, and its size says by how much.

`x = t/(2 τ)`

- **Often confused with:** **VNA**. A VNA measures the same reflections one frequency at a time. One inverse FFT turns them into a TDR trace.
- **In notes:** [Note 16, TDR](https://nearfieldnotes.com/notes/tdr/) · [Note 17, Via stubs](https://nearfieldnotes.com/notes/via-stubs/)

*What the figure shows:* Note 16's TDR trace of the USB 3 pair on the CM5 IO board at a 15 ps edge, impedance against mm from the socket pins. The route holds near 90 Ω. The socket pins dip to 67 Ω, and each via pair is a small bump. The arrow points at the dip.

Note 16's TDR on the USB 3 pair of Raspberry Pi's CM5 IO board, with a 15 ps edge. The socket pins dip to 67 Ω on the 90 Ω route.

### Thermal relief

Spokes that join a pin to a plane across a ring of bare board, so the plane can't pull away a soldering iron's heat.

- **Often confused with:** Antipad. An antipad keeps a pin off the plane. A relief joins them through spokes.
- **In notes:** [Note 7, Thermal relief](https://nearfieldnotes.com/notes/thermal-relief/)

*What the figure shows:* Note 7's header pin in a ground plane, top view, 4 mm across. With a relief, four 0.5 mm spokes cross a 0.5 mm gap and a 402 °C iron melts the far side in 3 s. Solid takes 536 °C. The arrow points at a spoke.

Note 7's header pin on a 4-layer board. The relief cuts the iron 134 °C cooler for the same 3 s melt.

## U

### Utilization

Of a SIMO’s inductor, in %

The share of time a SIMO’s inductor spends filling and emptying packets, counted over every rail. At 100% the packets run back to back, and any more load makes the rails droop.

`U = t_busy/t`

- **Often confused with:** Duty cycle. A duty cycle is one switch’s share of a fixed period. A SIMO has no fixed period, and its busy time counts every packet to every rail.
- **In notes:** [Note 22, SIMO converters](https://nearfieldnotes.com/notes/simo/)

*What the figure shows:* 30 µs of Note 22's inductor current at the watch's loads, run the datasheet's way: 10 humps, each a packet to one rail, with rests between. Under it, a strip marks the time the inductor is busy. Two packets near 25 µs run back to back. Over the whole run it is busy 28% of the time. The arrow points at the busy strip.

30 µs of Note 22’s inductor current at the watch’s loads, run the datasheet’s way, each packet in its rail’s color. Over the whole run it is busy 28% of the time.

## V

### VDM

Vendor-defined message, named by its SVID

A USB Power Delivery message on the CC wire that carries a 16-bit ID, its SVID, naming the standard or company it belongs to. Structured VDMs are how a host asks who the other end is and which modes it knows, then enters one.

- **Often confused with:** **Unstructured VDM**. An unstructured VDM sits outside the Discover and Enter steps. A Switch 2 and Nintendo’s dock trade more than 30 vendor messages before video.
- **In notes:** [Note 23, USB-C alt modes](https://nearfieldnotes.com/notes/usb-c-alt-modes/)

*What the figure shows:* A laptop and a monitor trading structured VDMs on the CC wire, as a ladder of messages: Discover Identity, answered with its vendor, product and type; Discover SVIDs, answered with FF01, DisplayPort's SVID; Discover Modes, answered with the pin assignments it can take; then Enter Mode, acknowledged. The arrow points at FF01.

The first eight messages of Note 23’s Fig. 23c, in the order of the USB Type-C and Power Delivery specs. FF01 is DisplayPort’s SVID.

### Via stub

The leftover length of a via's plated barrel below the layer the signal leaves on. It hangs off the line like a short wire with an open end, and notches the signal where it is a quarter wave long.

`f _notch = c/(4 L √(ε_r))`

- **Often confused with:** **Trace stub**. A trace stub is a branch of trace off the line, like the lead to a test pad. It rings the same way, but you can route it away. A via stub comes with the hole.
- **In notes:** [Note 8, Eye diagram](https://nearfieldnotes.com/notes/eye-diagram/) · [Note 16, TDR](https://nearfieldnotes.com/notes/tdr/) · [Note 17, Via stubs](https://nearfieldnotes.com/notes/via-stubs/)

*What the figure shows:* Note 17's via in section, to scale: a plated hole through a 1.58 mm, 6-layer board. The signal comes in on the top layer, runs down the barrel and leaves on layer 3. The barrel below layer 3, 0.94 mm of it, carries nothing on: the stub. The arrow points at it.

Note 17's via on the MNT Reform motherboard 3.0, from the top layer to layer 3, to scale. It leaves a 0.94 mm stub, which notches at 37.4 GHz.

## Z

### Zero-voltage switching

ZVS

Turning a switch on only after a current has already pulled the voltage across it to zero. With nothing across it, there is almost nothing to turn into heat.

`I ≥ Q/t_dead`

- **Often confused with:** **Valley switching**. Valley switching waits for the lowest point of the ring, which isn’t zero. Note 11’s silicon flyback still turns on at 78 V and dumps its drain’s charge.
- **In notes:** [Note 10, Zero-voltage switching](https://nearfieldnotes.com/notes/zvs/) · [Note 11, GaN vs silicon](https://nearfieldnotes.com/notes/gan-vs-si/)

*What the figure shows:* Note 10's FET turning on at 48 V and 10 A, voltage across it against time. Hard, it still has 48 V across it when its gate comes on at 50 ns. Zero-voltage, a current has already pulled it to zero. The arrow points there.

Note 10’s TPN19008QM at 48 V and 10 A, simulated in ngspice. Hard, 48 V is still across it as its gate comes on, and the turn-on loses 2.6 µJ. At zero volts it loses 0.45 µJ.

---

Source: https://nearfieldnotes.com/glossary/